[linux-yocto] [PATCH 04/39] LSI powerpc/boot: added for rapidio

Charlie Paul cpaul.windriver at gmail.com
Tue Apr 22 13:59:16 PDT 2014


---
 arch/arm/boot/dts/axm55xx.dts         |   33 +++
 arch/powerpc/boot/dts/lsi_acp342x.dts |  317 +++++++++++++++++++++++++++++
 arch/powerpc/boot/dts/lsi_acp344x.dts |  355 +++++++++++++++++++++++++++++++++
 3 files changed, 705 insertions(+)
 create mode 100644 arch/powerpc/boot/dts/lsi_acp342x.dts
 create mode 100644 arch/powerpc/boot/dts/lsi_acp344x.dts

diff --git a/arch/arm/boot/dts/axm55xx.dts b/arch/arm/boot/dts/axm55xx.dts
index 1aabe31..230a305 100644
--- a/arch/arm/boot/dts/axm55xx.dts
+++ b/arch/arm/boot/dts/axm55xx.dts
@@ -35,6 +35,8 @@
 		serial0	  = &axxia_serial0;
 		timer	  = &axxia_timers;
 		ethernet0 = &axxia_femac0;
+		rapidio0  = &rio0;
+		rapidio1  = &rio1;
 	};
 
 	cpus {
@@ -455,6 +457,37 @@
 		reg = <0x20 0x10098000 0 0x3000>;
 		interrupts = <0 45 4>;
 	};
+
+        rio0: rapidio at 0x3100000000 {
+                index = <0>;
+                status = "okay";
+                #address-cells = <2>;
+                #size-cells = <2>;
+                compatible = "axxia,rapidio-delta";
+                device_type = "rapidio";
+                reg = <0x0020 0x20142000 0x0 0x1000>; /* SRIO Conf 0 region */
+                ranges = <0x0 0x0 0x0031 0x00000000 0x0 0x40000000>;
+                linkdown-reset = <0x0200 0x100 0x0020 0x10000000 0x0 0x000010000>;
+                interrupts = <0 89 4>;
+                outb-dmes = <2 0x00000003 1 0x00000000>;
+		enable_ds = <1>;
+        };
+
+        rio1: rapidio at 0x3140000000 {
+                index = <1>;
+                status = "okay";
+                #address-cells = <2>;
+                #size-cells = <2>;
+                compatible = "axxia,rapidio-delta";
+                device_type = "rapidio";
+                reg = <0x0020 0x20143000 0x0 0x1000>; /* SRIO Conf 1 region */
+                ranges = <0x0 0x0 0x0031 0x40000000 0x0 0x40000000>;
+                linkdown-reset = <0x0200 0x200 0x0020 0x10000000 0x0 0x000010000>;
+                interrupts = <0 90 4>;
+                outb-dmes = <2 0x00000003 1 0x00000000>;
+		enable_ds = <1>;
+        };
+
 };
 
 /*
diff --git a/arch/powerpc/boot/dts/lsi_acp342x.dts b/arch/powerpc/boot/dts/lsi_acp342x.dts
new file mode 100644
index 0000000..da6066e
--- /dev/null
+++ b/arch/powerpc/boot/dts/lsi_acp342x.dts
@@ -0,0 +1,317 @@
+/*
+ * Device Tree Source for IBM Embedded PPC 476 Platform
+ *
+ * Copyright 2009 Torez Smith, IBM Corporation.
+ *
+ * Based on earlier code:
+ *     Copyright (c) 2006, 2007 IBM Corp.
+ *     Josh Boyer <jwboyer at linux.vnet.ibm.com>, David Gibson <dwg at au1.ibm.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without
+ * any warranty of any kind, whether express or implied.
+ */
+
+/dts-v1/;
+
+/memreserve/ 0x00000000 0x00400000;
+
+/ {
+	#address-cells = <2>;
+	#size-cells = <1>;
+	model = "ibm,acpx1-4xx";
+	compatible = "ibm,acpx1-4xx","ibm,47x-AMP";
+	dcr-parent = <&{/cpus/cpu at 0}>;
+
+	aliases {
+		serial0 = &UART0;
+		serial1 = &UART1;
+		rapidio0 = &rio0;
+		ethernet0 = &FEMAC;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu at 0 {
+			device_type = "cpu";
+			model = "PowerPC,4xx"; // real CPU changed in sim
+			reg = <0>;
+                        clock-frequency = <0x5f5e1000>;
+                        timebase-frequency = <0x5f5e1000>;
+			i-cache-line-size = <32>;
+			d-cache-line-size = <32>;
+			i-cache-size = <32768>;
+			d-cache-size = <32768>;
+			dcr-controller;
+			dcr-access-method = "native";
+			status = "ok";
+			reset-type = <3>; // 1=core, 2=chip, 3=system (default)
+		};
+		cpu at 1 {
+			device_type = "cpu";
+			model = "PowerPC,4xx"; // real CPU changed in sim
+			reg = <1>;
+                        clock-frequency = <0x5f5e1000>;
+                        timebase-frequency = <0x5f5e1000>;
+			i-cache-line-size = <32>;
+			d-cache-line-size = <32>;
+			i-cache-size = <32768>;
+			d-cache-size = <32768>;
+			dcr-controller;
+			dcr-access-method = "native";
+			status = "disabled";
+			enable-method = "spin-table";
+			cpu-release-addr = <0 0x2040>;
+			reset-type = <3>; // 1=core, 2=chip, 3=system (default)
+		};
+	};
+
+        memory at 0 {
+                device_type = "memory";
+                reg = <0x00000000 0x00000000 0x10000000>;
+        };
+
+        memory at 80000000 {
+                device_type = "memory";
+                reg = <0x00000000 0x00000000 0x00000000>;
+        };
+
+	MPIC: interrupt-controller {
+		compatible = "chrp,open-pic";
+		interrupt-controller;
+		dcr-reg = <0xffc00000 0x00030000>;
+		#address-cells = <0>;
+		#size-cells = <0>;
+		#interrupt-cells = <2>;
+		pic-no-reset;
+	};
+
+	plb {
+		/* Could be PLB6, doesn't matter */
+		compatible = "ibm,plb-4xx", "ibm,plb4";
+		#address-cells = <2>;
+		#size-cells = <1>;
+		ranges;
+		clock-frequency = <0>; // Filled in by zImage
+
+		POB0: opb {
+			compatible = "ibm,opb-4xx", "ibm,opb";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			/* Wish there was a nicer way of specifying a full 32-bit
+			   range */
+			ranges = <0x00000000 0x00000020 0x00000000 0x80000000
+				  0x80000000 0x00000020 0x80000000 0x80000000>;
+			clock-frequency = <0>; // Filled in by zImage
+			UART0: serial at 00404000 {
+				device_type = "serial";
+				compatible = "acp-uart0";
+				enabled = <1>;
+				reg = <0x00404000 0x1000>;
+				clock-reg = <0x00408040 0x20>;
+				clock-frequency = <200000000>;
+				current-speed = <9600>;
+				interrupt-parent = <&MPIC>;
+				interrupts = <22>;
+			};
+			UART1: serial at 00405000 {
+				device_type = "serial";
+				compatible = "acp-uart1";
+				enabled = <0>;
+				reg = <0x00405000 0x1000>;
+				clock-reg = <0x00408060 0x20>;
+				clock-frequency = <200000000>;
+				current-speed = <9600>;
+				interrupt-parent = <&MPIC>;
+				interrupts = <23>;
+			};
+			USB0: usb at 004a4000 {
+				device_type = "usb";
+				compatible = "acp-usb";
+				enabled = <0>;
+				reg = <0x004a4000 0x00020000>;
+				interrupt-parent = <&MPIC>;
+				interrupts = <31>;
+			};
+			I2C: i2c at 00403000 {
+				compatible = "acp-i2c";
+				enabled = <0>;
+				reg = <0x00403000 0x00001000>;
+				interrupt-parent = <&MPIC>;
+				interrupts = <21>;
+			};
+			SSP: ssp at 00402000 {
+				compatible = "acp-ssp";
+				enabled = <0>;
+				reg = <0x00402000 0x00001000>;
+				interrupt-parent = <&MPIC>;
+				interrupts = <20>;
+			};
+			NAND: nand at 00440000 {
+				device_type = "nand";
+				compatible = "acp-nand";
+				enabled = <1>;
+				reg = <0x00440000 0x20000
+				       0x0040c000 0x1000>;
+			};
+			FEMAC: femac at 00480000 {
+				device_type = "network";
+				compatible = "acp-femac";
+				enabled = <1>;
+				reg = <0x00480000 0x1000
+				       0x00481000 0x1000
+				       0x00482000 0x1000>;
+				interrupt-parent = <&MPIC>;
+				interrupts = <33>;
+				mdio-reg = <0x00409000 0x1000>;
+				// The following will get filled in by
+				// the boot loader.
+				mdio-clock = <0>;
+				phy-address = <0>;
+				ad-value = <0>;
+				mac-address = [00 00 00 00 00 00];
+			};
+		};
+	};
+
+
+	nvrtc {
+		compatible = "ds1743-nvram", "ds1743", "rtc-ds1743";
+		reg = <0 0xEF703000 0x2000>;
+	};
+
+	system {
+		ncr_0x00a_0x010_0x0002c = <0>; // filled in by the boot loader.
+		ncr_0x016_0x0ff_0x00010 = <0>; // filled in by the boot loader.
+	};
+
+	chosen {
+		linux,stdout-path = "/plb/opb/serial at 00404000";
+	};
+
+        PCIE0: pciex at f00c0000 {
+                compatible = "lsi,plb-pciex";
+                device_type = "pci";
+                enabled = <0>;
+                plx = <0>;
+                primary;
+                port = <0>;
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                /* config space access MPAGE7 registers*/
+                reg = <0x0020 0x78000000 0x01000000
+	               0x0020 0x004c0000 0x00008000 >;
+                bus-range = <0 0x0f>;
+                /* Outbound ranges */
+                /* < <3-cell PCI addr> <2-cell CPU (PLB) addr> <2-cell size> > */
+                ranges = <0x02000000 0x00000000 0xa0000000
+                          0x20 0x40000000
+                          0x00 0x10000000>;
+                /* Inbound ranges */
+                /* < <3-cell PCI addr> <2-cell CPU addr> <2-cell size> > */
+                dma-ranges = <0x02000000 0x00000000 0x00000000
+                              0x00 0x00000000
+                              0x00 0x10000000>;
+                    interrupt-parent = <&MPIC>;
+                interrupts = <29 2>;
+                interrupt-map-mask = <0000 0 0 7>;
+                interrupt-map = <
+                        /* <3-cell dev> <irq#> <prnt> <2-cell prnt IRQ/sense> */
+                        0000 0 0 1 &MPIC 29 2
+                        0000 0 0 2 &MPIC 29 2
+                        0000 0 0 3 &MPIC 29 2
+                        0000 0 0 4 &MPIC 29 2
+                >;
+        };
+
+        PCIE1: pciex at f00c8000 {
+                compatible = "lsi,plb-pciex";
+                device_type = "pci";
+                enabled = <0>;
+                plx = <0>;
+                primary;
+                port = <1>;
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                /* config space access MPAGE7 registers*/
+                reg = <0x0020 0xf8000000 0x01000000
+                       0x0020 0x004c8000 0x00008000 >;
+                bus-range = <0 0x0f>;
+                /* Outbound ranges */
+                /* < <3-cell PCI addr> <2-cell CPU (PLB) addr> <2-cell size> > */
+                ranges = <0x02000000 0x00000000 0xb0000000
+                          0x20 0xc0000000
+                          0x00 0x10000000>;
+                /* Inbound ranges */
+                /* < <3-cell PCI addr> <2-cell CPU addr> <2-cell size> > */
+                dma-ranges = <0x02000000 0x00000000 0x00000000
+                              0x00 0x00000000
+                              0x00 0x10000000>;
+                interrupt-parent = <&MPIC>;
+                interrupts = <72 2>;
+                interrupt-map-mask = <0000 0 0 7>;
+                interrupt-map = <
+                        /* <3-cell dev> <irq#> <prnt> <2-cell prnt IRQ/sense> */
+                        0000 0 0 1 &MPIC 72 2
+                        0000 0 0 2 &MPIC 72 2
+                        0000 0 0 3 &MPIC 72 2
+                        0000 0 0 4 &MPIC 72 2
+                >;
+        };
+
+        PCIE2: pciex at f00d0000 {
+                compatible = "lsi,plb-pciex";
+                device_type = "pci";
+                enabled = <0>;
+                plx = <0>;
+                primary;
+                port = <2>;
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                /* config space access MPAGE7 registers*/
+                reg = <0x0021 0x38000000 0x01000000
+                       0x0020 0x004d0000 0x00008000 >;
+                bus-range = <0 0x0f>;
+                /* Outbound ranges */
+                /* < <3-cell PCI addr> <2-cell CPU (PLB) addr> <2-cell size> > */
+                ranges = <0x02000000 0x00000000 0xc0000000
+                          0x21 0x00000000
+                          0x00 0x10000000>;
+                /* Inbound ranges */
+                /* < <3-cell PCI addr> <2-cell CPU addr> <2-cell size> > */
+                dma-ranges = <0x02000000 0x00000000 0x00000000
+                              0x00 0x00000000
+                              0x00 0x10000000>;
+
+                interrupt-parent = <&MPIC>;
+                interrupts = <73 2>;
+                interrupt-map-mask = <0000 0 0 7>;
+                interrupt-map = <
+                        /* <3-cell dev> <irq#> <prnt> <2-cell prnt IRQ/sense> */
+                        0000 0 0 1 &MPIC 73 2
+                        0000 0 0 2 &MPIC 73 2
+                        0000 0 0 3 &MPIC 73 2
+                        0000 0 0 4 &MPIC 73 2
+                >;
+        };
+
+	rio0: rapidio {
+                index = <0>;
+		status = "ok";
+                #address-cells = <2>;
+                #size-cells = <2>;
+		compatible = "acp,rapidio-delta";
+                device_type = "rapidio";
+		reg = <0x0020 0x00420000 0x1000>; /* SRIO Conf region */
+                ranges = <0x0 0x0 0x0020 0x80000000 0x0 0x40000000>;
+		interrupt-parent = <&MPIC>;
+		interrupts = <30 0x2 /* NCP_INTR_MPIC_SRC_AXIS_SRIO */>;
+                outb-dmes = <2 0x00000003 1 0x00000000>; /* X7 Defect 44844 */
+	};
+
+};
diff --git a/arch/powerpc/boot/dts/lsi_acp344x.dts b/arch/powerpc/boot/dts/lsi_acp344x.dts
new file mode 100644
index 0000000..63d49f5
--- /dev/null
+++ b/arch/powerpc/boot/dts/lsi_acp344x.dts
@@ -0,0 +1,355 @@
+/*
+ * Device Tree Source for IBM Embedded PPC 476 Platform
+ *
+ * Copyright 2009 Torez Smith, IBM Corporation.
+ *
+ * Based on earlier code:
+ *     Copyright (c) 2006, 2007 IBM Corp.
+ *     Josh Boyer <jwboyer at linux.vnet.ibm.com>, David Gibson <dwg at au1.ibm.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without
+ * any warranty of any kind, whether express or implied.
+ */
+
+/dts-v1/;
+
+/memreserve/ 0x00000000 0x00400000;
+
+/ {
+        #address-cells = <2>;
+        #size-cells = <1>;
+        model = "ibm,acpx1-4xx";
+        compatible = "ibm,acpx1-4xx","ibm,47x-AMP";
+        dcr-parent = <&{/cpus/cpu at 0}>;
+
+        aliases {
+                serial0 = &UART0;
+                serial1 = &UART1;
+                rapidio0 = &rio0;
+		ethernet0 = &FEMAC;
+        };
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu at 0 {
+                        device_type = "cpu";
+                        model = "PowerPC,4xx"; // real CPU changed in sim
+                        reg = <0>;
+                        clock-frequency = <0x5f5e1000>;
+                        timebase-frequency = <0x5f5e1000>;
+                        i-cache-line-size = <32>;
+                        d-cache-line-size = <32>;
+                        i-cache-size = <32768>;
+                        d-cache-size = <32768>;
+                        dcr-controller;
+                        dcr-access-method = "native";
+                        status = "ok";
+                        reset-type = <3>; // 1=core, 2=chip, 3=system (default)
+                };
+                cpu at 1 {
+                        device_type = "cpu";
+                        model = "PowerPC,4xx"; // real CPU changed in sim
+                        reg = <1>;
+                        clock-frequency = <0x5f5e1000>;
+                        timebase-frequency = <0x5f5e1000>;
+                        i-cache-line-size = <32>;
+                        d-cache-line-size = <32>;
+                        i-cache-size = <32768>;
+                        d-cache-size = <32768>;
+                        dcr-controller;
+                        dcr-access-method = "native";
+                        status = "disabled";
+                        enable-method = "spin-table";
+                        cpu-release-addr = <0 0x2040>;
+                        reset-type = <3>; // 1=core, 2=chip, 3=system (default)
+                };
+                cpu at 2 {
+                        device_type = "cpu";
+                        model = "PowerPC,4xx"; // real CPU changed in sim
+                        reg = <2>;
+                        clock-frequency = <0x5f5e1000>;
+                        timebase-frequency = <0x5f5e1000>;
+                        i-cache-line-size = <32>;
+                        d-cache-line-size = <32>;
+                        i-cache-size = <32768>;
+                        d-cache-size = <32768>;
+                        dcr-controller;
+                        dcr-access-method = "native";
+                        status = "disabled";
+                        enable-method = "spin-table";
+                        cpu-release-addr = <0 0x2080>;
+                        reset-type = <3>; // 1=core, 2=chip, 3=system (default)
+                };
+                cpu at 3 {
+                        device_type = "cpu";
+                        model = "PowerPC,4xx"; // real CPU changed in sim
+                        reg = <3>;
+                        clock-frequency = <0x5f5e1000>;
+                        timebase-frequency = <0x5f5e1000>;
+                        i-cache-line-size = <32>;
+                        d-cache-line-size = <32>;
+                        i-cache-size = <32768>;
+                        d-cache-size = <32768>;
+                        dcr-controller;
+                        dcr-access-method = "native";
+                        status = "disabled";
+                        enable-method = "spin-table";
+                        cpu-release-addr = <0 0x20c0>;
+                        reset-type = <3>; // 1=core, 2=chip, 3=system (default)
+                };
+        };
+
+        memory at 0 {
+                device_type = "memory";
+                reg = <0x00000000 0x00000000 0x80000000>; // filled in by U-Boot
+        };
+
+        memory at 80000000 {
+                device_type = "memory";
+                reg = <0x00000000 0x80000000 0x80000000>; // filled in by U-Boot
+        };
+
+        MPIC: interrupt-controller {
+                compatible = "chrp,open-pic";
+                interrupt-controller;
+                dcr-reg = <0xffc00000 0x00030000>;
+                #address-cells = <0>;
+                #size-cells = <0>;
+                #interrupt-cells = <2>;
+                pic-no-reset;
+        };
+
+        plb {
+                /* Could be PLB6, doesn't matter */
+                compatible = "ibm,plb-4xx", "ibm,plb4";
+                #address-cells = <2>;
+                #size-cells = <1>;
+                ranges;
+                clock-frequency = <0>; // Filled in by zImage
+
+                POB0: opb {
+                        compatible = "ibm,opb-4xx", "ibm,opb";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        /* Wish there was a nicer way of specifying a full 32-bit
+                           range */
+                        ranges = <0x00000000 0x00000020 0x00000000 0x80000000
+                                  0x80000000 0x00000020 0x80000000 0x80000000>;
+                        clock-frequency = <0>; // Filled in by zImage
+                        UART0: serial at 00404000 {
+                                device_type = "serial";
+                                compatible = "acp-uart0";
+                                enabled = <1>;
+                                reg = <0x00404000 0x1000>;
+                                clock-reg = <0x00408040 0x20>;
+                                clock-frequency = <0xbebc200>;
+                                current-speed = <9600>;
+                                interrupt-parent = <&MPIC>;
+                                interrupts = <22>;
+                        };
+                        UART1: serial at 00405000 {
+                                device_type = "serial";
+                                compatible = "acp-uart1";
+                                enabled = <0>;
+                                reg = <0x00405000 0x1000>;
+                                clock-reg = <0x00408060 0x20>;
+                                clock-frequency = <200000000>;
+                                current-speed = <9600>;
+                                interrupt-parent = <&MPIC>;
+                                interrupts = <23>;
+                        };
+                        USB0: usb at 004a4000 {
+                                device_type = "usb";
+                                compatible = "acp-usb";
+                                enabled = <0>;
+                                reg = <0x004a4000 0x00020000>;
+                                interrupt-parent = <&MPIC>;
+                                interrupts = <31>;
+                        };
+                        I2C: i2c at 00403000 {
+                                compatible = "acp-i2c";
+                                enabled = <0>;
+                                reg = <0x00403000 0x00001000>;
+                                interrupt-parent = <&MPIC>;
+                                interrupts = <21>;
+                        };
+                        SSP: ssp at 00402000 {
+                                compatible = "acp-ssp";
+                                enabled = <0>;
+                                reg = <0x00402000 0x00001000>;
+                                interrupt-parent = <&MPIC>;
+                                interrupts = <20>;
+                        };
+                        NAND: nand at 00440000 {
+                                device_type = "nand";
+                                compatible = "acp-nand";
+                                enabled = <1>;
+                                reg = <0x00440000 0x20000
+                                       0x0040c000 0x1000>;
+                        };
+                        FEMAC: femac at 00480000 {
+                                device_type = "network";
+                                compatible = "acp-femac";
+                                enabled = <1>;
+                                reg = <0x00480000 0x1000
+                                       0x00481000 0x1000
+                                       0x00482000 0x1000>;
+                                interrupt-parent = <&MPIC>;
+                                interrupts = <33>;
+                                mdio-reg = <0x00409000 0x1000>;
+                                // The following will get filled in by
+                                // the boot loader.
+                                mdio-clock = <0>;
+                                phy-address = <0>;
+                                ad-value = <0>;
+                                mac-address = [00 00 00 00 00 00];
+                        };
+                };
+        };
+
+
+        nvrtc {
+                compatible = "ds1743-nvram", "ds1743", "rtc-ds1743";
+                reg = <0 0xEF703000 0x2000>;
+        };
+
+        system {
+                ncr_0x00a_0x010_0x0002c = <0>; // filled in by the boot loader.
+                ncr_0x016_0x0ff_0x00010 = <0>; // filled in by the boot loader.
+        };
+
+        chosen {
+                linux,stdout-path = "/plb/opb/serial at 00404000";
+        };
+
+        PCIE0: pciex at f00c0000 {
+                compatible = "lsi,plb-pciex";
+                device_type = "pci";
+                enabled = <0>;
+                plx = <0>;
+                primary;
+                port = <0>;
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                /* config space access MPAGE7 registers*/
+                reg = < 0x0020 0x78000000 0x01000000
+                0x0020 0x004c0000 0x00008000 >;
+                bus-range = <0 0x0f>;
+                /* Outbound ranges */
+                /* < <3-cell PCI addr> <2-cell CPU (PLB) addr> <2-cell size> > */
+                ranges = <0x02000000 0x00000000 0xa0000000
+                          0x20 0x40000000
+                          0x00 0x10000000>;
+                /* Inbound ranges */
+                /* < <3-cell PCI addr> <2-cell CPU addr> <2-cell size> > */
+                dma-ranges = <0x02000000 0x00000000 0x00000000
+                              0x00 0x00000000
+                              0x00 0x10000000>;
+                    interrupt-parent = <&MPIC>;
+                interrupts = <29 2>;
+                interrupt-map-mask = <0000 0 0 7>;
+                interrupt-map = <
+                        /* <3-cell dev> <irq#> <prnt> <2-cell prnt IRQ/sense> */
+                        0000 0 0 1 &MPIC 29 2
+                        0000 0 0 2 &MPIC 29 2
+                        0000 0 0 3 &MPIC 29 2
+                        0000 0 0 4 &MPIC 29 2
+                >;
+        };
+
+        PCIE1: pciex at f00c8000 {
+                compatible = "lsi,plb-pciex";
+                device_type = "pci";
+                enabled = <0>;
+                plx = <0>;
+                primary;
+                port = <1>;
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                /* config space access MPAGE7 registers*/
+                reg = <0x0020 0xf8000000 0x01000000
+                       0x0020 0x004c8000 0x00008000 >;
+                bus-range = <0 0x0f>;
+                /* Outbound ranges */
+                /* < <3-cell PCI addr> <2-cell CPU (PLB) addr> <2-cell size> > */
+                ranges = <0x02000000 0x00000000 0xa0000000
+                          0x20 0xc0000000
+                          0x00 0x10000000>;
+                /* Inbound ranges */
+                /* < <3-cell PCI addr> <2-cell CPU addr> <2-cell size> > */
+                dma-ranges = <0x02000000 0x00000000 0x00000000
+                              0x00 0x00000000
+                              0x00 0x10000000>;
+                interrupt-parent = <&MPIC>;
+                interrupts = <72 2>;
+                interrupt-map-mask = <0000 0 0 7>;
+                interrupt-map = <
+                        /* <3-cell dev> <irq#> <prnt> <2-cell prnt IRQ/sense> */
+                        0000 0 0 1 &MPIC 72 2
+                        0000 0 0 2 &MPIC 72 2
+                        0000 0 0 3 &MPIC 72 2
+                        0000 0 0 4 &MPIC 72 2
+                >;
+        };
+
+        PCIE2: pciex at f00d0000 {
+                compatible = "lsi,plb-pciex";
+                device_type = "pci";
+                enabled = <0>;
+                plx = <0>;
+                primary;
+                port = <2>;
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                /* config space access MPAGE7 registers*/
+                reg = <0x0021 0x38000000 0x01000000
+                       0x0020 0x004d0000 0x00008000 >;
+                bus-range = <0 0x0f>;
+                /* Outbound ranges */
+                /* < <3-cell PCI addr> <2-cell CPU (PLB) addr> <2-cell size> > */
+                ranges = <0x02000000 0x00000000 0xa0000000
+                          0x21 0x00000000
+                          0x00 0x10000000>;
+                /* Inbound ranges */
+                /* < <3-cell PCI addr> <2-cell CPU addr> <2-cell size> > */
+                dma-ranges = <0x02000000 0x00000000 0x00000000
+                              0x00 0x00000000
+                              0x00 0x10000000>;
+
+                interrupt-parent = <&MPIC>;
+                interrupts = <73 2>;
+                interrupt-map-mask = <0000 0 0 7>;
+                interrupt-map = <
+                        /* <3-cell dev> <irq#> <prnt> <2-cell prnt IRQ/sense> */
+                        0000 0 0 1 &MPIC 73 2
+                        0000 0 0 2 &MPIC 73 2
+                        0000 0 0 3 &MPIC 73 2
+                        0000 0 0 4 &MPIC 73 2
+                >;
+        };
+
+	rio0: rapidio at f0020000{
+                index = <0>;
+		status = "ok";
+                #address-cells = <3>;
+                #size-cells = <2>;
+                compatible = "acp,rapidio-delta";
+                device_type = "rapidio";
+                reg = <0x0020 0x00420000 0x1000>; /* SRIO Conf region */
+                ranges = <0x0 0x0 0x0020 0x80000000 0x0 0x40000000>;
+                interrupt-parent = <&MPIC>;
+                interrupts = <30 0x2 /* NCP_INTR_MPIC_SRC_AXIS_SRIO */>;
+                outb-dmes = <2 0x00000003 1 0x00000000>; /* X7 Defect 44844 */
+		enable_ds = <1>;
+		inb-dse = <0x00000020 0x00000400 0x00000100>; /* virt_m, data, dbuf */
+		/* inb-dse = <0x00000002 0x00000020 0x00000020>; */
+		outb-dse = <0x00000010 0x00000400 0x00000400 0x00000010>; /*dse,hdr,data,dbuf */
+		/* outb-dse = <0x00000002 0x00000020 0x00000020 0x00000020>; */
+        };
+};
-- 
1.7.9.5



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