[linux-yocto] [PATCH 2/6] x86/byt: enable board file for Baytrail LPSS PCI mode

[rebecca.swee.fun.chang at intel.com]

From: Chang Rebecca Swee Fun <rebecca.swee.fun.chang at intel.com>

This commit enables the following:
- register SPI slave
- insert kernel module param to allow user to disable the BYT
  PCI board file

Signed-off-by: Chew Chiau Ee <chiau.ee.chew at intel.com>
Signed-off-by: Maurice Petallo <mauricex.r.petallo at intel.com>
Signed-off-by: Chang Rebecca Swee Fun <rebecca.swee.fun.chang at intel.com>
---
 arch/x86/Kconfig                  |  9 +++++-
 arch/x86/platform/Makefile        |  3 ++
 arch/x86/platform/byt/Makefile    |  1 +
 arch/x86/platform/byt/byt-board.c | 59 +++++++++++++++++++++++++++++++++++++++
 4 files changed, 71 insertions(+), 1 deletion(-)
 create mode 100644 arch/x86/platform/byt/Makefile
 create mode 100644 arch/x86/platform/byt/byt-board.c

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index f92273e..7a72641 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -460,7 +460,7 @@ config X86_MDFLD
 	select MFD_INTEL_MSIC
 	---help---
 	  Medfield is Intel's Low Power Intel Architecture (LPIA) based Moblin
-	  Internet Device(MID) platform. 
+	  Internet Device(MID) platform.
 	  Unlike standard x86 PCs, Medfield does not have many legacy devices
 	  nor standard legacy replacement devices/features. e.g. Medfield does
 	  not contain i8259, i8254, HPET, legacy BIOS, most of the io ports.
@@ -478,6 +478,13 @@ config X86_INTEL_LPSS
 	  things like clock tree (common clock framework) and pincontrol
 	  which are needed by the LPSS peripheral drivers.
 
+config BYT_LPSS_BRD
+	bool "PCI mode LPSS support on BYT"
+	depends on X86_INTEL_LPSS
+	---help---
+	  This option is needed if were to use Intel BayTrail LPSS in
+	  PCI mode.
+
 config X86_RDC321X
 	bool "RDC R-321x SoC"
 	depends on X86_32
diff --git a/arch/x86/platform/Makefile b/arch/x86/platform/Makefile
index 01e0231..da0017b 100644
--- a/arch/x86/platform/Makefile
+++ b/arch/x86/platform/Makefile
@@ -11,3 +11,6 @@ obj-y	+= sfi/
 obj-y	+= ts5500/
 obj-y	+= visws/
 obj-y	+= uv/
+ifeq ($(CONFIG_BYT_LPSS_BRD),y)
+obj-y   += byt/
+endif
diff --git a/arch/x86/platform/byt/Makefile b/arch/x86/platform/byt/Makefile
new file mode 100644
index 0000000..2d4af86
--- /dev/null
+++ b/arch/x86/platform/byt/Makefile
@@ -0,0 +1 @@
+obj-y    += byt-board.o
diff --git a/arch/x86/platform/byt/byt-board.c b/arch/x86/platform/byt/byt-board.c
new file mode 100644
index 0000000..4841f89
--- /dev/null
+++ b/arch/x86/platform/byt/byt-board.c
@@ -0,0 +1,59 @@
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/device.h>
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
+#include <linux/spi/spidev.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/pxa2xx_spi.h>
+#include <linux/pwm.h>
+
+static bool disable = 0;
+module_param(disable, bool, 0);
+MODULE_PARM_DESC(disable, "set 1 to disable BYT brd file");
+
+static struct pxa2xx_spi_chip chip_data = {
+	.gpio_cs = -EINVAL,
+	.dma_burst_size = 32,
+};
+
+static struct spi_board_info byt_spi_slaves[] = {
+	{
+	.modalias = "spidev",
+	.max_speed_hz = 50000000,
+	.bus_num = 0,
+	.chip_select = 0,
+	.controller_data = &chip_data,
+	.mode = SPI_MODE_0,
+	}
+};
+
+static int byt_spi_board_setup(void)
+{
+	int ret = -1;
+
+	/* Register the SPI devices */
+	if (!spi_register_board_info
+		(byt_spi_slaves, ARRAY_SIZE(byt_spi_slaves)))
+		ret = 0;
+
+	return ret;
+}
+
+static int __init byt_board_init(void)
+{
+	int ret;
+
+	if (disable)
+		return 0;
+
+	ret = byt_spi_board_setup();
+	if (ret)
+		goto exit;
+
+exit:
+	return ret;
+}
+arch_initcall(byt_board_init);
+MODULE_LICENSE(GPL);
-- 
1.9.1