[linux-yocto] [PATCH 6/9] MIPS Override assembler ISA for kernel FPU instruction.

[Abhishek Paliwal]

From: David Daney <david.daney at cavium.com>

Some versions of the assembler will not assemble CFC1 for OCTEON, so
override the ISA for these.

Signed-off-by: David Daney <david.daney at cavium.com>
Signed-off-by: Abhishek Paliwal <abhishek.paliwal at aricent.com>
---
 arch/mips/kernel/ptrace.c   | 24 ++++++++++++++++++++----
 arch/mips/kernel/ptrace32.c | 12 ++++++++++--
 2 files changed, 30 insertions(+), 6 deletions(-)

diff --git a/arch/mips/kernel/ptrace.c b/arch/mips/kernel/ptrace.c
index 60f48fe..ef22c14 100644
--- a/arch/mips/kernel/ptrace.c
+++ b/arch/mips/kernel/ptrace.c
@@ -138,13 +138,21 @@ int ptrace_getfpregs(struct task_struct *child, __u32 __user *data)
                        unsigned int vpflags = dvpe();
                        flags = read_c0_status();
                        __enable_fpu(FPU_AS_IS);
-                       __asm__ __volatile__("cfc1\t%0,$0" : "=r" (tmp));
+                       __asm__ __volatile__(
+                               ".set push\n"
+                               "\t.set mips1\n"
+                               "\tcfc1\t%0,$0\n"
+                               "\t.set pop" : "=r" (tmp));
                        write_c0_status(flags);
                        evpe(vpflags);
                } else {
                        flags = read_c0_status();
                        __enable_fpu(FPU_AS_IS);
-                       __asm__ __volatile__("cfc1\t%0,$0" : "=r" (tmp));
+                       __asm__ __volatile__(
+                               ".set push\n"
+                               "\t.set mips1\n"
+                               "\tcfc1\t%0,$0\n"
+                               "\t.set pop" : "=r" (tmp));
                        write_c0_status(flags);
                }
        } else {
@@ -619,13 +627,21 @@ long arch_ptrace(struct task_struct *child, long request,
                                unsigned int vpflags = dvpe();
                                flags = read_c0_status();
                                __enable_fpu(FPU_AS_IS);
-                               __asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp));
+                               __asm__ __volatile__(
+                                       ".set push\n"
+                                       "\t.set mips1\n"
+                                       "\tcfc1\t%0,$0\n"
+                                       "\t.set pop" : "=r" (tmp));
                                write_c0_status(flags);
                                evpe(vpflags);
                        } else {
                                flags = read_c0_status();
                                __enable_fpu(FPU_AS_IS);
-                               __asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp));
+                               __asm__ __volatile__(
+                                       ".set push\n"
+                                       "\t.set mips1\n"
+                                       "\tcfc1\t%0,$0\n"
+                                       "\t.set pop" : "=r" (tmp));
                                write_c0_status(flags);
                        }
 #ifdef CONFIG_MIPS_MT_SMTC
diff --git a/arch/mips/kernel/ptrace32.c b/arch/mips/kernel/ptrace32.c
index b8aa2dd..b7c5ad6 100644
--- a/arch/mips/kernel/ptrace32.c
+++ b/arch/mips/kernel/ptrace32.c
@@ -153,13 +153,21 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request,
                                unsigned int vpflags = dvpe();
                                flags = read_c0_status();
                                __enable_fpu(FPU_AS_IS);
-                               __asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp));
+                               __asm__ __volatile__(
+                                       ".set push\n"
+                                       "\t.set mips1\n"
+                                       "\tcfc1\t%0,$0\n"
+                                       "\t.set pop" : "=r" (tmp));
                                write_c0_status(flags);
                                evpe(vpflags);
                        } else {
                                flags = read_c0_status();
                                __enable_fpu(FPU_AS_IS);
-                               __asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp));
+                               __asm__ __volatile__(
+                                       ".set push\n"
+                                       "\t.set mips1\n"
+                                       "\tcfc1\t%0,$0\n"
+                                       "\t.set pop" : "=r" (tmp));
                                write_c0_status(flags);
                        }
 #ifdef CONFIG_MIPS_MT_SMTC
--
1.8.1.4



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