[linux-yocto] [PATCH 7/9] MIPS: Octeon: Implement the core-16057 workaround

[Chandrakala Chavva]

From: Abhishek Paliwal <abhishek.paliwal at aricent.com>

From: David Daney <david.daney at cavium.com>

Disable ICache prefetch for certian Octeon II processors.

Signed-off-by: David Daney <david.daney at cavium.com>
Signed-off-by: Abhishek Paliwal <abhishek.paliwal at aricent.com>
---
 .../asm/mach-cavium-octeon/kernel-entry-init.h     | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h b/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
index 1668ee5..0030c80 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
@@ -63,6 +63,28 @@ skip:
 	li	v1, ~(7 << 7)
 	and	v0, v0, v1
 	ori	v0, v0, (6 << 7)
+
+	mfc0    v1, CP0_PRID_REG
+	and     t1, v1, 0xfff8
+	xor     t1, t1, 0x9000          # 63-P1
+	beqz    t1, 4f
+	and     t1, v1, 0xfff8
+	xor     t1, t1, 0x9008          # 63-P2
+	beqz    t1, 4f
+	and     t1, v1, 0xfff8
+	xor     t1, t1, 0x9100          # 68-P1
+	beqz    t1, 4f
+	and     t1, v1, 0xff00
+	xor     t1, t1, 0x9200          # 66-PX
+	bnez    t1, 5f                  # Skip WAR for others.
+	and     t1, v1, 0x00ff
+	slti    t1, t1, 2               # 66-P1.2 and later good.
+	beqz    t1, 5f
+
+4 :	# core-16057 work around
+	or      v0, v0, 0x2000          # Set IPREF bit.
+
+5 :	# No core-16057 work around
 	# Write the cavium control register
 	dmtc0	v0, CP0_CVMCTL_REG
 	sync
-- 
1.8.1.4