[linux-yocto] [PATCH 08/13] MIPS/OCTEON: TLB parity error handling

[Chandrakala Chavva]

From: Abhishek Paliwal <abhishek.paliwal at aricent.com>

From: David Daney <david.daney at cavium.com>

We need to temporarily disable TLB Parity checks early in the handler
so we don't get into an endless loop.

The meaning of cvmmemctl[44] changed, 0 means enabled.

Bug #8300

Signed-off-by: David Daney <david.daney at cavium.com>
Signed-off-by: Leonid Rosenboim <lrosenboim at caviumnetworks.com>
Signed-off-by: Chandrakala Chavva <cchavva at caviumnetworks.com>
Signed-off-by: Abhishek Paliwal <abhishek.paliwal at aricent.com>
---
 arch/mips/kernel/genex.S | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S
index d84f6a5..03a878c 100644
--- a/arch/mips/kernel/genex.S
+++ b/arch/mips/kernel/genex.S
@@ -404,6 +404,26 @@ NESTED(nmi_handler, PT_SIZE, sp)
 	TRACE_IRQS_OFF
 	.endm
 
+	.macro  __build_clear_mce
+#ifdef CONFIG_CPU_CAVIUM_OCTEON
+	/* Disable TLB Parity checks. */
+	mfc0    t2, $15,0
+	and     t2, 0xff00
+	dli     t0, 0x9500
+	/* In Octeon3 setting bit 44 disables TLB parity */
+	slt     t2, t2, t0
+	dmfc0   t0, $11, 7
+	dli     t1, (1 << 44)
+	or      t0, t0, t1
+	beqz    t2, 11f
+	nop
+	xor     t0, t0, t1
+11 :
+	dmtc0   t0, $11, 7
+#endif
+	__build_clear_cli
+	.endm
+
 	.macro	__build_clear_fpe
 	.set	push
 	/* gas fails to assemble cfc1 for some archs (octeon).*/ \
-- 
1.8.1.4