[linux-yocto] [PATCH 49/52] arch/arm/mach-axxia: Add Support for Big Endian
Daniel Dragomir
daniel.dragomir at windriver.com
Wed Jan 28 09:19:03 PST 2015
From: John Jacques <john.jacques at lsi.com>
Signed-off-by: John Jacques <john.jacques at lsi.com>
---
arch/arm/Kconfig | 2 +
arch/arm/Makefile | 6 ++-
arch/arm/include/asm/assembler.h | 7 ++++
arch/arm/include/asm/hardware/debug-pl01x.S | 6 ++-
arch/arm/kernel/entry-armv.S | 6 +--
arch/arm/kernel/entry-common.S | 4 +-
arch/arm/kernel/head.S | 43 +++++++++++++------
arch/arm/kernel/kprobes.c | 4 +-
arch/arm/kernel/module.c | 65 ++++++++++++++++++-----------
arch/arm/kernel/sleep.S | 1 +
arch/arm/kernel/smp_scu.c | 14 +++----
arch/arm/kernel/smp_twd.c | 25 ++++++-----
arch/arm/mach-axxia/headsmp.S | 2 +
arch/arm/mach-axxia/platsmp.c | 6 ++-
arch/arm/mach-ixp4xx/Kconfig | 4 --
arch/arm/mm/Kconfig | 6 +++
arch/arm/mm/abort-ev6.S | 4 +-
arch/arm/mm/proc-v6.S | 4 +-
arch/arm/mm/proc-v7.S | 4 +-
arch/arm/plat-versatile/headsmp.S | 2 +
drivers/net/ethernet/lsi/lsi_acp_mdio.c | 6 +--
drivers/net/ethernet/lsi/lsi_acp_net.c | 16 +++++--
drivers/net/ethernet/lsi/lsi_acp_net.h | 12 +++---
include/linux/mtd/map.h | 16 +++----
24 files changed, 162 insertions(+), 103 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 63a4e06..c766c5f 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -353,6 +353,7 @@ config ARCH_AXXIA
select ARCH_PHYS_ADDR_T_64BIT
select ARCH_DMA_ADDR_T_64BIT
select ARCH_WANT_OPTIONAL_GPIOLIB
+ select ARCH_SUPPORTS_BIG_ENDIAN
select ARM_AMBA
select COMMON_CLK
select CLKDEV_LOOKUP
@@ -499,6 +500,7 @@ config ARCH_IXP4XX
depends on MMU
select ARCH_HAS_DMA_SET_COHERENT_MASK
select ARCH_REQUIRE_GPIOLIB
+ select ARCH_SUPPORTS_BIG_ENDIAN
select CLKSRC_MMIO
select CPU_XSCALE
select DMABOUNCE if PCI
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 992f213..42cfd77 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -16,6 +16,7 @@ LDFLAGS :=
LDFLAGS_vmlinux :=-p --no-undefined -X
ifeq ($(CONFIG_CPU_ENDIAN_BE8),y)
LDFLAGS_vmlinux += --be8
+LDFLAGS_MODULE += --be8
endif
OBJCOPYFLAGS :=-O binary -R .comment -S
@@ -45,8 +46,9 @@ endif
ifeq ($(CONFIG_CPU_BIG_ENDIAN),y)
KBUILD_CPPFLAGS += -mbig-endian
-AS += -EB
-LD += -EB
+#AS += -EB
+#LD += -EB
+LDFLAGS += -EB
else
KBUILD_CPPFLAGS += -mlittle-endian
AS += -EL
diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h
index 05ee9ee..e780afb 100644
--- a/arch/arm/include/asm/assembler.h
+++ b/arch/arm/include/asm/assembler.h
@@ -53,6 +53,13 @@
#define put_byte_3 lsl #0
#endif
+/* Select code for any configuration running in BE8 mode */
+#ifdef CONFIG_CPU_ENDIAN_BE8
+#define ARM_BE8(code...) code
+#else
+#define ARM_BE8(code...)
+#endif
+
/*
* Data preload for architectures that support it
*/
diff --git a/arch/arm/include/asm/hardware/debug-pl01x.S b/arch/arm/include/asm/hardware/debug-pl01x.S
index f9fd083..d58f63e 100644
--- a/arch/arm/include/asm/hardware/debug-pl01x.S
+++ b/arch/arm/include/asm/hardware/debug-pl01x.S
@@ -17,13 +17,15 @@
.endm
.macro waituart,rd,rx
-1001: ldr \rd, [\rx, #UART01x_FR]
+1001: ldr \rd, [\rx, #UART01x_FR]
+ARM_BE8(rev \rd, \rd)
tst \rd, #UART01x_FR_TXFF
bne 1001b
.endm
.macro busyuart,rd,rx
-1001: ldr \rd, [\rx, #UART01x_FR]
+1001: ldr \rd, [\rx, #UART01x_FR]
+ARM_BE8(rev \rd, \rd)
tst \rd, #UART01x_FR_BUSY
bne 1001b
.endm
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index 32640ae..d1ad01e 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -416,9 +416,7 @@ __und_usr:
bne __und_usr_thumb
sub r4, r2, #4 @ ARM instr at LR - 4
1: ldrt r0, [r4]
-#ifdef CONFIG_CPU_ENDIAN_BE8
- rev r0, r0 @ little endian instruction
-#endif
+ARM_BE8(rev r0, r0) @ little endian instruction
@ r0 = 32-bit ARM instruction which caused the exception
@ r2 = PC value for the following instruction (:= regs->ARM_pc)
@ r4 = PC value for the faulting instruction
@@ -451,9 +449,11 @@ __und_usr_thumb:
.arch armv6t2
#endif
2: ldrht r5, [r4]
+ARM_BE8(rev16 r5, r5) @ get little endian inst in BE8.
cmp r5, #0xe800 @ 32bit instruction if xx != 0
blo __und_usr_fault_16 @ 16bit undefined instruction
3: ldrht r0, [r2]
+ARM_BE8(rev16 r0, r0) @ get little endian inst in BE8.
add r2, r2, #2 @ r2 is PC + 2, make it PC + 4
str r2, [sp, #S_PC] @ it's a 2x16bit instr, update
orr r0, r0, r5, lsl #16
diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S
index aaad7b8..109bccb 100644
--- a/arch/arm/kernel/entry-common.S
+++ b/arch/arm/kernel/entry-common.S
@@ -389,9 +389,7 @@ ENTRY(vector_swi)
#else
USER( ldr r10, [lr, #-4] ) @ get SWI instruction
#endif
-#ifdef CONFIG_CPU_ENDIAN_BE8
- rev r10, r10 @ little endian instruction
-#endif
+ARM_BE8(rev r10, r10) @ little endian instruction
#elif defined(CONFIG_AEABI)
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index 4234b36..12df7f7 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -82,6 +82,8 @@
__HEAD
ENTRY(stext)
+ARM_BE8(setend be) @ ensure we are in BE8 mode
+
THUMB( adr r9, BSYM(1f) ) @ Kernel is always entered in ARM.
THUMB( bx r9 ) @ If this is a Thumb-2 kernel,
@@ -295,19 +297,29 @@ __create_page_tables:
orr r3, r7, r3, lsl #SECTION_SHIFT
#ifdef CONFIG_ARM_LPAE
mov r7, #1 << (54 - 32) @ XN
-#ifdef CONFIG_CPU_ENDIAN_BE8
- str r7, [r0], #4
- str r3, [r0], #4
-#else
- str r3, [r0], #4
- str r7, [r0], #4
-#endif
+ #ifdef CONFIG_CPU_ENDIAN_BE8
+ str r7, [r0], #4
+ str r3, [r0], #4
+ #else
+ str r3, [r0], #4
+ str r7, [r0], #4
+ #endif
#else
- orr r3, r3, #PMD_SECT_XN
-#ifdef CONFIG_ARCH_AXXIA
- orr r7, r7, #0x20
-#endif
- str r3, [r0], #4
+ //orr r3, r3, #PMD_SECT_XN
+ #ifdef CONFIG_ARCH_AXXIA
+ orr r7, r7, #0x20
+ #endif
+1:
+ #ifdef CONFIG_CPU_ENDIAN_BE8
+ str r7, [r0], #4
+ str r3, [r0], #4
+ #else
+ str r3, [r0], #4
+ str r7, [r0], #4
+ #endif /* CONFIG_CPU_ENDIAN_BE8 */
+ add r3, r3, #1 << SECTION_SHIFT
+ cmp r0, r6
+ blo 1b
#endif
#else /* CONFIG_DEBUG_ICEDCC || CONFIG_DEBUG_SEMIHOSTING */
@@ -364,6 +376,7 @@ ENTRY(secondary_startup)
#endif
safe_svcmode_maskall r9
+ARM_BE8(setend be) @ if system starts LE, go BE8
mrc p15, 0, r9, c0, c0 @ get processor id
bl __lookup_processor_type
movs r10, r5 @ invalid processor?
@@ -602,8 +615,14 @@ __fixup_a_pv_table:
#else
b 2f
1: ldr ip, [r7, r3]
+#ifdef CONFIG_CPU_ENDIAN_BE8
+ @ in BE8, we load data in BE, but instructions still in LE
+ bic ip, ip, #0xff000000
+ orr ip, ip, r6, lsl#24
+#else
bic ip, ip, #0x000000ff
orr ip, ip, r6 @ mask in offset bits 31-24
+#endif
str ip, [r7, r3]
2: cmp r4, r5
ldrcc r7, [r4], #4 @ use branch for delay slot
diff --git a/arch/arm/kernel/kprobes.c b/arch/arm/kernel/kprobes.c
index 1c6ece5..e505a9a 100644
--- a/arch/arm/kernel/kprobes.c
+++ b/arch/arm/kernel/kprobes.c
@@ -63,10 +63,10 @@ int __kprobes arch_prepare_kprobe(struct kprobe *p)
#ifdef CONFIG_THUMB2_KERNEL
thumb = true;
addr &= ~1; /* Bit 0 would normally be set to indicate Thumb code */
- insn = __mem_to_opcode_thumb16(((u16 *)addr)[0]);
+ insn = __opcode_to_mem_thumb16(((u16 *)addr)[0]);
if (is_wide_instruction(insn)) {
u16 inst2 = __mem_to_opcode_thumb16(((u16 *)addr)[1]);
- insn = __opcode_thumb32_compose(insn, inst2);
+ insn = ___asm_opcode_thumb32_compose(insn, inst2);
decode_insn = thumb32_kprobe_decode_insn;
} else
decode_insn = thumb16_kprobe_decode_insn;
diff --git a/arch/arm/kernel/module.c b/arch/arm/kernel/module.c
index 1e9be5d..2cf9b54 100644
--- a/arch/arm/kernel/module.c
+++ b/arch/arm/kernel/module.c
@@ -24,6 +24,7 @@
#include <asm/sections.h>
#include <asm/smp_plat.h>
#include <asm/unwind.h>
+#include <asm/opcodes.h>
#ifdef CONFIG_XIP_KERNEL
/*
@@ -63,6 +64,7 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex,
#ifdef CONFIG_THUMB2_KERNEL
u32 upper, lower, sign, j1, j2;
#endif
+ u32 instr32;
offset = ELF32_R_SYM(rel->r_info);
if (offset < 0 || offset > (symsec->sh_size / sizeof(Elf32_Sym))) {
@@ -95,7 +97,8 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex,
case R_ARM_PC24:
case R_ARM_CALL:
case R_ARM_JUMP24:
- offset = (*(u32 *)loc & 0x00ffffff) << 2;
+ instr32 = __mem_to_opcode_arm(*(u32 *)loc);
+ offset = (instr32 & 0x00ffffff) << 2;
if (offset & 0x02000000)
offset -= 0x04000000;
@@ -112,8 +115,9 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex,
offset >>= 2;
- *(u32 *)loc &= 0xff000000;
- *(u32 *)loc |= offset & 0x00ffffff;
+ *(u32 *)loc =
+ __opcode_to_mem_arm((instr32 & 0xff000000) |
+ (offset & 0x00ffffff));
break;
case R_ARM_V4BX:
@@ -121,9 +125,9 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex,
* other bits to re-code instruction as
* MOV PC,Rm.
*/
- *(u32 *)loc &= 0xf000000f;
- *(u32 *)loc |= 0x01a0f000;
- break;
+ instr32 = __mem_to_opcode_arm(*(u32 *)loc) & 0xf000000f;
+ *(u32 *)loc = __opcode_to_mem_arm(instr32 | 0x01a0f000);
+ break;
case R_ARM_PREL31:
offset = *(u32 *)loc + sym->st_value - loc;
@@ -132,7 +136,7 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex,
case R_ARM_MOVW_ABS_NC:
case R_ARM_MOVT_ABS:
- offset = *(u32 *)loc;
+ offset = __mem_to_opcode_arm(*(u32 *)loc);
offset = ((offset & 0xf0000) >> 4) | (offset & 0xfff);
offset = (offset ^ 0x8000) - 0x8000;
@@ -140,16 +144,17 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex,
if (ELF32_R_TYPE(rel->r_info) == R_ARM_MOVT_ABS)
offset >>= 16;
- *(u32 *)loc &= 0xfff0f000;
- *(u32 *)loc |= ((offset & 0xf000) << 4) |
- (offset & 0x0fff);
+ instr32 = __mem_to_opcode_arm(*(u32 *)loc) & 0xfff0f000;
+ *(u32 *)loc = __opcode_to_mem_arm(instr32 |
+ ((offset & 0xf000) << 4) |
+ (offset & 0x0fff));
break;
#ifdef CONFIG_THUMB2_KERNEL
case R_ARM_THM_CALL:
case R_ARM_THM_JUMP24:
- upper = *(u16 *)loc;
- lower = *(u16 *)(loc + 2);
+ upper = __mem_to_opcode_thumb16(*(u16 *)loc);
+ lower = __mem_to_opcode_thumb16(*(u16 *)(loc + 2));
/*
* 25 bit signed address range (Thumb-2 BL and B.W
@@ -198,17 +203,23 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex,
sign = (offset >> 24) & 1;
j1 = sign ^ (~(offset >> 23) & 1);
j2 = sign ^ (~(offset >> 22) & 1);
- *(u16 *)loc = (u16)((upper & 0xf800) | (sign << 10) |
- ((offset >> 12) & 0x03ff));
- *(u16 *)(loc + 2) = (u16)((lower & 0xd000) |
- (j1 << 13) | (j2 << 11) |
- ((offset >> 1) & 0x07ff));
+
+ *(u16 *)loc = __opcode_to_mem_thumb16((u16)(
+ (upper & 0xf800) |
+ (sign << 10) |
+ ((offset >> 12) & 0x03ff)
+ ));
+ *(u16 *)(loc + 2) = __opcode_to_mem_thumb16((u16)(
+ (lower & 0xd000) |
+ (j1 << 13) | (j2 << 11) |
+ ((offset >> 1) & 0x07ff)
+ ));
break;
case R_ARM_THM_MOVW_ABS_NC:
case R_ARM_THM_MOVT_ABS:
- upper = *(u16 *)loc;
- lower = *(u16 *)(loc + 2);
+ upper = __mem_to_opcode_thumb16(*(u16 *)loc);
+ lower = __mem_to_opcode_thumb16(*(u16 *)(loc + 2));
/*
* MOVT/MOVW instructions encoding in Thumb-2:
@@ -229,12 +240,16 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex,
if (ELF32_R_TYPE(rel->r_info) == R_ARM_THM_MOVT_ABS)
offset >>= 16;
- *(u16 *)loc = (u16)((upper & 0xfbf0) |
- ((offset & 0xf000) >> 12) |
- ((offset & 0x0800) >> 1));
- *(u16 *)(loc + 2) = (u16)((lower & 0x8f00) |
- ((offset & 0x0700) << 4) |
- (offset & 0x00ff));
+ *(u16 *)loc = __opcode_to_mem_thumb16((u16)(
+ (upper & 0xfbf0) |
+ ((offset & 0xf000) >> 12) |
+ ((offset & 0x0800) >> 1)
+ ));
+ *(u16 *)(loc + 2) = __opcode_to_mem_thumb16((u16)(
+ (lower & 0x8f00) |
+ ((offset & 0x0700) << 4) |
+ (offset & 0x00ff)
+ ));
break;
#endif
diff --git a/arch/arm/kernel/sleep.S b/arch/arm/kernel/sleep.S
index 987dcf3..954c28a 100644
--- a/arch/arm/kernel/sleep.S
+++ b/arch/arm/kernel/sleep.S
@@ -81,6 +81,7 @@ ENDPROC(cpu_resume_after_mmu)
.data
.align
ENTRY(cpu_resume)
+ARM_BE8(setend be) @ ensure we are in BE mode
#ifdef CONFIG_SMP
adr r0, sleep_save_sp
ALT_SMP(mrc p15, 0, r1, c0, c0, 5)
diff --git a/arch/arm/kernel/smp_scu.c b/arch/arm/kernel/smp_scu.c
index 5bc1a63..1aafa0d 100644
--- a/arch/arm/kernel/smp_scu.c
+++ b/arch/arm/kernel/smp_scu.c
@@ -28,7 +28,7 @@
*/
unsigned int __init scu_get_core_count(void __iomem *scu_base)
{
- unsigned int ncores = __raw_readl(scu_base + SCU_CONFIG);
+ unsigned int ncores = readl_relaxed(scu_base + SCU_CONFIG);
return (ncores & 0x03) + 1;
}
@@ -42,19 +42,19 @@ void scu_enable(void __iomem *scu_base)
#ifdef CONFIG_ARM_ERRATA_764369
/* Cortex-A9 only */
if ((read_cpuid_id() & 0xff0ffff0) == 0x410fc090) {
- scu_ctrl = __raw_readl(scu_base + 0x30);
+ scu_ctrl = readl_relaxed(scu_base + 0x30);
if (!(scu_ctrl & 1))
- __raw_writel(scu_ctrl | 0x1, scu_base + 0x30);
+ writel_relaxed(scu_ctrl | 0x1, scu_base + 0x30);
}
#endif
- scu_ctrl = __raw_readl(scu_base + SCU_CTRL);
+ scu_ctrl = readl_relaxed(scu_base + SCU_CTRL);
/* already enabled? */
if (scu_ctrl & 1)
return;
scu_ctrl |= 1;
- __raw_writel(scu_ctrl, scu_base + SCU_CTRL);
+ writel_relaxed(scu_ctrl, scu_base + SCU_CTRL);
/*
* Ensure that the data accessed by CPU0 before the SCU was
@@ -80,9 +80,9 @@ int scu_power_mode(void __iomem *scu_base, unsigned int mode)
if (mode > 3 || mode == 1 || cpu > 3)
return -EINVAL;
- val = __raw_readb(scu_base + SCU_CPU_STATUS + cpu) & ~0x03;
+ val = readb_relaxed(scu_base + SCU_CPU_STATUS + cpu) & ~0x03;
val |= mode;
- __raw_writeb(val, scu_base + SCU_CPU_STATUS + cpu);
+ writeb_relaxed(val, scu_base + SCU_CPU_STATUS + cpu);
return 0;
}
diff --git a/arch/arm/kernel/smp_twd.c b/arch/arm/kernel/smp_twd.c
index f6fd1d4..b50be8d 100644
--- a/arch/arm/kernel/smp_twd.c
+++ b/arch/arm/kernel/smp_twd.c
@@ -45,8 +45,7 @@ static void twd_set_mode(enum clock_event_mode mode,
case CLOCK_EVT_MODE_PERIODIC:
ctrl = TWD_TIMER_CONTROL_ENABLE | TWD_TIMER_CONTROL_IT_ENABLE
| TWD_TIMER_CONTROL_PERIODIC;
- __raw_writel(DIV_ROUND_CLOSEST(twd_timer_rate, HZ),
- twd_base + TWD_TIMER_LOAD);
+ writel_relaxed(twd_timer_rate / HZ, twd_base + TWD_TIMER_LOAD);
break;
case CLOCK_EVT_MODE_ONESHOT:
/* period set, and timer enabled in 'next_event' hook */
@@ -58,18 +57,18 @@ static void twd_set_mode(enum clock_event_mode mode,
ctrl = 0;
}
- __raw_writel(ctrl, twd_base + TWD_TIMER_CONTROL);
+ writel_relaxed(ctrl, twd_base + TWD_TIMER_CONTROL);
}
static int twd_set_next_event(unsigned long evt,
struct clock_event_device *unused)
{
- unsigned long ctrl = __raw_readl(twd_base + TWD_TIMER_CONTROL);
+ unsigned long ctrl = readl_relaxed(twd_base + TWD_TIMER_CONTROL);
ctrl |= TWD_TIMER_CONTROL_ENABLE;
- __raw_writel(evt, twd_base + TWD_TIMER_COUNTER);
- __raw_writel(ctrl, twd_base + TWD_TIMER_CONTROL);
+ writel_relaxed(evt, twd_base + TWD_TIMER_COUNTER);
+ writel_relaxed(ctrl, twd_base + TWD_TIMER_CONTROL);
return 0;
}
@@ -82,8 +81,8 @@ static int twd_set_next_event(unsigned long evt,
*/
static int twd_timer_ack(void)
{
- if (__raw_readl(twd_base + TWD_TIMER_INTSTAT)) {
- __raw_writel(1, twd_base + TWD_TIMER_INTSTAT);
+ if (readl_relaxed(twd_base + TWD_TIMER_INTSTAT)) {
+ writel_relaxed(1, twd_base + TWD_TIMER_INTSTAT);
return 1;
}
@@ -209,15 +208,15 @@ static void __cpuinit twd_calibrate_rate(void)
waitjiffies += 5;
/* enable, no interrupt or reload */
- __raw_writel(0x1, twd_base + TWD_TIMER_CONTROL);
+ writel_relaxed(0x1, twd_base + TWD_TIMER_CONTROL);
/* maximum value */
- __raw_writel(0xFFFFFFFFU, twd_base + TWD_TIMER_COUNTER);
+ writel_relaxed(0xFFFFFFFFU, twd_base + TWD_TIMER_COUNTER);
while (get_jiffies_64() < waitjiffies)
udelay(10);
- count = __raw_readl(twd_base + TWD_TIMER_COUNTER);
+ count = readl_relaxed(twd_base + TWD_TIMER_COUNTER);
twd_timer_rate = (0xFFFFFFFFU - count) * (HZ / 5);
@@ -275,7 +274,7 @@ static int __cpuinit twd_timer_setup(struct clock_event_device *clk)
* bother with the below.
*/
if (per_cpu(percpu_setup_called, cpu)) {
- __raw_writel(0, twd_base + TWD_TIMER_CONTROL);
+ writel_relaxed(0, twd_base + TWD_TIMER_CONTROL);
clockevents_register_device(*__this_cpu_ptr(twd_evt));
enable_percpu_irq(clk->irq, 0);
return 0;
@@ -288,7 +287,7 @@ static int __cpuinit twd_timer_setup(struct clock_event_device *clk)
* The following is done once per CPU the first time .setup() is
* called.
*/
- __raw_writel(0, twd_base + TWD_TIMER_CONTROL);
+ writel_relaxed(0, twd_base + TWD_TIMER_CONTROL);
clk->name = "local_timer";
clk->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT |
diff --git a/arch/arm/mach-axxia/headsmp.S b/arch/arm/mach-axxia/headsmp.S
index b4fe409..c51373d 100644
--- a/arch/arm/mach-axxia/headsmp.S
+++ b/arch/arm/mach-axxia/headsmp.S
@@ -12,6 +12,7 @@
*/
#include <linux/linkage.h>
#include <linux/init.h>
+#include <asm/assembler.h>
__CPUINIT
@@ -21,6 +22,7 @@
* ready for them to initialise.
*/
ENTRY(axxia_secondary_startup)
+ARM_BE8(setend be)
mrc p15, 0, r0, c0, c0, 5
bic r0, #0xff000000
adr r4, 1f
diff --git a/arch/arm/mach-axxia/platsmp.c b/arch/arm/mach-axxia/platsmp.c
index 2804fce..70981ee8 100644
--- a/arch/arm/mach-axxia/platsmp.c
+++ b/arch/arm/mach-axxia/platsmp.c
@@ -287,13 +287,17 @@ static void __init axxia_smp_prepare_cpus(unsigned int max_cpus)
*/
if (release_phys != 0) {
int is_kmapped = pfn_valid(__phys_to_pfn(release_phys));
+
if (is_kmapped)
release_virt = phys_to_virt(release_phys);
else
release_virt = ioremap(release_phys, PAGE_SIZE);
- *release_virt = virt_to_phys(axxia_secondary_startup);
+
+ writel_relaxed(virt_to_phys(axxia_secondary_startup),
+ release_virt);
smp_wmb();
__cpuc_flush_dcache_area(release_virt, sizeof(u32));
+
if (!is_kmapped)
iounmap(release_virt);
}
diff --git a/arch/arm/mach-ixp4xx/Kconfig b/arch/arm/mach-ixp4xx/Kconfig
index 73a2d90..72de05f 100644
--- a/arch/arm/mach-ixp4xx/Kconfig
+++ b/arch/arm/mach-ixp4xx/Kconfig
@@ -1,9 +1,5 @@
if ARCH_IXP4XX
-config ARCH_SUPPORTS_BIG_ENDIAN
- bool
- default y
-
menu "Intel IXP4xx Implementation Options"
comment "IXP4xx Platforms"
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index c6926ea..2e71959 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -932,3 +932,9 @@ config ARCH_HAS_BARRIERS
help
This option allows the use of custom mandatory barriers
included via the mach/barriers.h file.
+
+config ARCH_SUPPORTS_BIG_ENDIAN
+ bool
+ help
+ This option specifies the architecture can support big endian
+ operation.
diff --git a/arch/arm/mm/abort-ev6.S b/arch/arm/mm/abort-ev6.S
index 5d777a5..b2f6e1b 100644
--- a/arch/arm/mm/abort-ev6.S
+++ b/arch/arm/mm/abort-ev6.S
@@ -32,9 +32,7 @@ ENTRY(v6_early_abort)
bne do_DataAbort
bic r1, r1, #1 << 11 @ clear bit 11 of FSR
ldr r3, [r4] @ read aborted ARM instruction
-#ifdef CONFIG_CPU_ENDIAN_BE8
- rev r3, r3
-#endif
+ARM_BE8(rev r3, r3)
do_ldrd_abort tmp=ip, insn=r3
tst r3, #1 << 20 @ L = 0 -> write
orreq r1, r1, #1 << 11 @ yes.
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index d073528..d1a3e18 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -219,9 +219,7 @@ __v6_setup:
@ complete invalidations
adr r5, v6_crval
ldmia r5, {r5, r6}
-#ifdef CONFIG_CPU_ENDIAN_BE8
- orr r6, r6, #1 << 25 @ big-endian page tables
-#endif
+ARM_BE8(orr r6, r6, #1 << 25) @ big-endian page tables
mrc p15, 0, r0, c1, c0, 0 @ read control register
bic r0, r0, r5 @ clear bits them
orr r0, r0, r6 @ set them
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 4562ebf..763182a 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -350,9 +350,7 @@ __v7_setup:
#endif
adr r5, v7_crval
ldmia r5, {r5, r6}
-#ifdef CONFIG_CPU_ENDIAN_BE8
- orr r6, r6, #1 << 25 @ big-endian page tables
-#endif
+ARM_BE8(orr r6, r6, #1 << 25) @ big-endian page tables
#ifdef CONFIG_SWP_EMULATE
orr r5, r5, #(1 << 10) @ set SW bit in "clear"
bic r6, r6, #(1 << 10) @ clear it in "mmuset"
diff --git a/arch/arm/plat-versatile/headsmp.S b/arch/arm/plat-versatile/headsmp.S
index b178d44..e154a62 100644
--- a/arch/arm/plat-versatile/headsmp.S
+++ b/arch/arm/plat-versatile/headsmp.S
@@ -10,6 +10,7 @@
*/
#include <linux/linkage.h>
#include <linux/init.h>
+#include <asm/assembler.h>
__INIT
@@ -19,6 +20,7 @@
* until we're ready for them to initialise.
*/
ENTRY(versatile_secondary_startup)
+ARM_BE8(setend be)
mrc p15, 0, r0, c0, c0, 5
bic r0, #0xff000000
adr r4, 1f
diff --git a/drivers/net/ethernet/lsi/lsi_acp_mdio.c b/drivers/net/ethernet/lsi/lsi_acp_mdio.c
index b11011f..7bde921 100644
--- a/drivers/net/ethernet/lsi/lsi_acp_mdio.c
+++ b/drivers/net/ethernet/lsi/lsi_acp_mdio.c
@@ -38,12 +38,12 @@ static DEFINE_SPINLOCK(mdio_lock);
#ifdef CONFIG_ARM
static u32 read_reg(u32 *addr)
{
- return readl((void __iomem *)addr);
+ return readl_relaxed((void __iomem *)addr);
}
static void write_reg(u32 *addr, u32 value)
{
- writel(value, (void __iomem *)addr);
+ writel_relaxed(value, (void __iomem *)addr);
}
#else
static u32 read_reg(u32 *addr)
@@ -304,7 +304,7 @@ acp_mdio_init(void)
goto error;
}
- mdio_size = field[1];
+ mdio_size = field[3];
map = ioremap(mdio_address, mdio_size);
if (!map) {
diff --git a/drivers/net/ethernet/lsi/lsi_acp_net.c b/drivers/net/ethernet/lsi/lsi_acp_net.c
index b20e5fa..1973e04 100644
--- a/drivers/net/ethernet/lsi/lsi_acp_net.c
+++ b/drivers/net/ethernet/lsi/lsi_acp_net.c
@@ -682,13 +682,21 @@ static void lsinet_rx_packet(struct net_device *dev)
readdescriptor(((unsigned long)pdata->rx_desc +
pdata->rx_tail_copy.bits.offset), &descriptor);
- sk_buff = dev_alloc_skb(LSINET_MAX_MTU);
+ sk_buff = netdev_alloc_skb(NULL, LSINET_MAX_MTU);
if ((struct sk_buff *)0 == sk_buff) {
pr_info_ratelimited("%s: No buffer, packet dropped.\n",
LSI_DRV_NAME);
pdata->stats.rx_dropped++;
return;
+ } else {
+ /*
+ Needs to be reviewed. This fixed an aligment
+ exception when pinging to the target from a host.
+ */
+
+ /* Align IP on 16 byte boundaries */
+ skb_reserve(sk_buff, 2);
}
ok_stat = read_mac(APPNIC_RX_STAT_PACKET_OK);
@@ -1707,15 +1715,15 @@ static int appnic_probe_config_dt(struct net_device *dev,
goto device_tree_failed;
value64 = of_translate_address(np, field);
- value32 = field[1];
+ value32 = field[3];
field += 2;
pdata->rx_base = ioremap(value64, value32);
value64 = of_translate_address(np, field);
- value32 = field[1];
+ value32 = field[3];
field += 2;
pdata->tx_base = ioremap(value64, value32);
value64 = of_translate_address(np, field);
- value32 = field[1];
+ value32 = field[3];
field += 2;
pdata->dma_base = ioremap(value64, value32);
diff --git a/drivers/net/ethernet/lsi/lsi_acp_net.h b/drivers/net/ethernet/lsi/lsi_acp_net.h
index b943cd0..ac891cf 100644
--- a/drivers/net/ethernet/lsi/lsi_acp_net.h
+++ b/drivers/net/ethernet/lsi/lsi_acp_net.h
@@ -490,7 +490,12 @@ struct appnic_device {
#define read_mac(address) readl((void __iomem *)(address))
#define write_mac(value, address) writel((value), (void __iomem *)(address))
+#else
+#define read_mac(address) in_le32((u32 *) (address))
+#define write_mac(value, address) out_le32((u32 *) (address), (value))
+#endif /* CONFIG_ARM */
+#ifdef __LITTLE_ENDIAN
static inline void
readdescriptor(unsigned long address, struct appnic_dma_descriptor *descriptor)
{
@@ -504,7 +509,7 @@ writedescriptor(unsigned long address,
const struct appnic_dma_descriptor *descriptor)
{
memcpy((void *)address, descriptor,
- sizeof(struct appnic_dma_descriptor));
+ sizeof(struct appnic_dma_descriptor));
return;
}
@@ -523,9 +528,6 @@ femac_uncache(struct appnic_device *pdata)
#else
-#define read_mac(address) in_le32((u32 *) (address))
-#define write_mac(value, address) out_le32((u32 *) (address), (value))
-
static inline void
readdescriptor(unsigned long address, struct appnic_dma_descriptor *descriptor)
{
@@ -564,7 +566,7 @@ _swab_queue_pointer(const union appnic_queue_pointer *old_queue)
static inline void
femac_uncache(struct appnic_device *pdata) {}
-#endif /* ifdef CONFIG_ARM */
+#endif /* ifdef __LITTLE_ENDIAN */
static int
femac_irq_setup(struct net_device *dev)
diff --git a/include/linux/mtd/map.h b/include/linux/mtd/map.h
index 5f487d7..5520909 100644
--- a/include/linux/mtd/map.h
+++ b/include/linux/mtd/map.h
@@ -397,14 +397,14 @@ static inline map_word inline_map_read(struct map_info *map, unsigned long ofs)
map_word r;
if (map_bankwidth_is_1(map))
- r.x[0] = __raw_readb(map->virt + ofs);
+ r.x[0] = readb_relaxed(map->virt + ofs);
else if (map_bankwidth_is_2(map))
- r.x[0] = __raw_readw(map->virt + ofs);
+ r.x[0] = readw_relaxed(map->virt + ofs);
else if (map_bankwidth_is_4(map))
- r.x[0] = __raw_readl(map->virt + ofs);
+ r.x[0] = readl_relaxed(map->virt + ofs);
#if BITS_PER_LONG >= 64
else if (map_bankwidth_is_8(map))
- r.x[0] = __raw_readq(map->virt + ofs);
+ r.x[0] = readq_relaxed(map->virt + ofs);
#endif
else if (map_bankwidth_is_large(map))
memcpy_fromio(r.x, map->virt+ofs, map->bankwidth);
@@ -417,14 +417,14 @@ static inline map_word inline_map_read(struct map_info *map, unsigned long ofs)
static inline void inline_map_write(struct map_info *map, const map_word datum, unsigned long ofs)
{
if (map_bankwidth_is_1(map))
- __raw_writeb(datum.x[0], map->virt + ofs);
+ writeb_relaxed(datum.x[0], map->virt + ofs);
else if (map_bankwidth_is_2(map))
- __raw_writew(datum.x[0], map->virt + ofs);
+ writew_relaxed(datum.x[0], map->virt + ofs);
else if (map_bankwidth_is_4(map))
- __raw_writel(datum.x[0], map->virt + ofs);
+ writel_relaxed(datum.x[0], map->virt + ofs);
#if BITS_PER_LONG >= 64
else if (map_bankwidth_is_8(map))
- __raw_writeq(datum.x[0], map->virt + ofs);
+ writeq_relaxed(datum.x[0], map->virt + ofs);
#endif
else if (map_bankwidth_is_large(map))
memcpy_toio(map->virt+ofs, datum.x, map->bankwidth);
--
1.8.1.4
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