[linux-yocto] [PATCH 00/17] [linux-yocto-3.19] standard/base: Backport Braswell bug fixes patches from mainline to solve issue related to GFX's DRM/i915

[Bruce Ashfield]

On 2015-05-11 05:49 AM, wei.tee.ng at intel.com wrote:
> From: Ng Wei Tee <wei.tee.ng at intel.com>
>
> Hi all,
>
> This patch is to backport Braswell bug fixes patches that are
> available in the upstream kernel into Yocto Project linux kernel
> v3.19. These fixes are related to GFX's DRM/i915 kernel module.
>
> The fixes here fix the following scenarios:-
> 1) Single mode DPC goes to blank for resolution higher than
> 1920x1080 on Console
> 2) Single mode DPC/DPD goes into blank after S3 operation.
> 3) Dual DP boots on console with blanks on DPC goes into blank
> upon connecting to 1920x1200 native resolution.
> 4) Dual DP will get into blank after performing S3 multiple times
> especially greater than 1920x1080 resolutions.
>
> This configuration was built and tested working on CherryHill
> platform. Please review and provide feedback if any.
>
> This patch is target for linux-yocto-3.19 on standard/base branch.

The changes look fine to me. I've merged and pushed them to the
repository.

SRCREV updates to follow, but you can update locally to test.

Bruce

>
> Thanks.
>
> Regards,
> Wei Tee
> The following changes since commit 0a0d499541e2bb13ecc1001d0947bed6106c26a6:
>
>    Revert "intel_idle: Add support for the Airmont Core in the Cherrytrail and Braswell SOCs" (2015-05-05 13:11:34 -0400)
>
> are available in the git repository at:
>
>    git://git.yoctoproject.org/linux-yocto-contrib weitee/gfx-patch
>    http://git.yoctoproject.org/cgit.cgi/linux-yocto-contrib/log/?h=weitee/gfx-patch
>
> Clint Taylor (1):
>    drm/i915/chv: Remove DPIO force latency causing interpair skew issue
>
> Deepak S (1):
>    drm/i915: Increase the range of sideband address.
>
> Vidya Srinivas (1):
>    drm/i915: Program PFI credits for VLV
>
> Ville Syrjälä (14):
>    drm/i915: Reduce CHV DPLL min vco frequency to 4.8 GHz
>    drm/i915: Allow pixel clock up to 95% of cdclk on CHV
>    drm/i915: Reduce CHV DDL multiplier to 16/8
>    drm/i915: Kill DRAIN_LATENCY_PRECISION_* defines
>    drm/i915: Simplify VLV drain latency computation
>    drm/i915: Hide VLV DDL precision handling
>    drm/i915: Reorganize VLV DDL setup
>    drm/i915: Pass plane to vlv_compute_drain_latency()
>    drm/i915: Read out display FIFO size on VLV/CHV
>    drm/i915: Make sure PND deadline mode is enabled on VLV/CHV
>    drm/i915: Rewrite VLV/CHV watermark code
>    drm/i915: Enable the maxfifo PM5 mode when appropriate on CHV
>    drm/i915: Disable DDR DVFS on CHV
>    drm/i915: Fix chv cdclk support
>
>   drivers/gpu/drm/i915/i915_drv.h       |   24 +-
>   drivers/gpu/drm/i915/i915_reg.h       |   39 ++-
>   drivers/gpu/drm/i915/intel_display.c  |   75 +++--
>   drivers/gpu/drm/i915/intel_dp.c       |    5 -
>   drivers/gpu/drm/i915/intel_hdmi.c     |    5 -
>   drivers/gpu/drm/i915/intel_pm.c       |  533 ++++++++++++++++++++-------------
>   drivers/gpu/drm/i915/intel_sideband.c |    4 +-
>   7 files changed, 429 insertions(+), 256 deletions(-)
>