[linux-yocto] [PATCH 09/38] drivers/mtd: Changes to support the axxia BSP
Cristian Bercaru
cristian.bercaru at windriver.com
Wed May 20 12:23:52 PDT 2015
From: Charlie Paul <cpaul.windriver at gmail.com>
These files add mtd support for the axxia 5500
board.
Signed-off-by: Charlie Paul <cpaul.windriver at gmail.com>
---
drivers/mtd/devices/m25p80.c | 23 +-
drivers/mtd/nand/Kconfig | 13 +
drivers/mtd/nand/Makefile | 2 +
drivers/mtd/nand/lsi_acp_nand.c | 3678 +++++++++++++++++++++++++++++++++++++++
drivers/mtd/nand/lsi_ubootenv.c | 570 ++++++
drivers/mtd/spi-nor/spi-nor.c | 17 +-
include/linux/lsi_mtc_ioctl.h | 72 +
7 files changed, 4358 insertions(+), 17 deletions(-)
create mode 100644 drivers/mtd/nand/lsi_acp_nand.c
create mode 100644 drivers/mtd/nand/lsi_ubootenv.c
create mode 100644 include/linux/lsi_mtc_ioctl.h
diff --git a/drivers/mtd/devices/m25p80.c b/drivers/mtd/devices/m25p80.c
index 85e35467..e43d3dfe 100644
--- a/drivers/mtd/devices/m25p80.c
+++ b/drivers/mtd/devices/m25p80.c
@@ -134,7 +134,7 @@ static int m25p80_read(struct spi_nor *nor, loff_t from, size_t len,
dummy /= 8;
spi_message_init(&m);
- memset(t, 0, (sizeof t));
+ memset(t, 0, (sizeof(t)));
flash->command[0] = nor->read_opcode;
m25p_addr2cmd(nor, from, flash->command);
@@ -259,26 +259,27 @@ static const struct spi_device_id m25p_ids[] = {
{"en25q64"}, {"en25qh128"}, {"en25qh256"},
{"f25l32pa"},
{"mr25h256"}, {"mr25h10"},
+ {"mb85rs1mt"},
{"gd25q32"}, {"gd25q64"},
{"160s33b"}, {"320s33b"}, {"640s33b"},
{"mx25l2005a"}, {"mx25l4005a"}, {"mx25l8005"}, {"mx25l1606e"},
{"mx25l3205d"}, {"mx25l3255e"}, {"mx25l6405d"}, {"mx25l12805d"},
- {"mx25l12855e"},{"mx25l25635e"},{"mx25l25655e"},{"mx66l51235l"},
+ {"mx25l12855e"}, {"mx25l25635e"}, {"mx25l25655e"}, {"mx66l51235l"},
{"mx66l1g55g"},
- {"n25q064"}, {"n25q128a11"}, {"n25q128a13"}, {"n25q256a"},
- {"n25q512a"}, {"n25q512ax3"}, {"n25q00"},
+ {"n25q032"}, {"n25q064"}, {"n25q128a11"}, {"n25q128a13"},
+ {"n25q256a"}, {"n25q512a"}, {"n25q512ax3"}, {"n25q00"},
{"pm25lv512"}, {"pm25lv010"}, {"pm25lq032"},
{"s25sl032p"}, {"s25sl064p"}, {"s25fl256s0"}, {"s25fl256s1"},
{"s25fl512s"}, {"s70fl01gs"}, {"s25sl12800"}, {"s25sl12801"},
- {"s25fl129p0"}, {"s25fl129p1"}, {"s25sl004a"}, {"s25sl008a"},
- {"s25sl016a"}, {"s25sl032a"}, {"s25sl064a"}, {"s25fl008k"},
- {"s25fl016k"}, {"s25fl064k"}, {"s25fl132k"},
- {"sst25vf040b"},{"sst25vf080b"},{"sst25vf016b"},{"sst25vf032b"},
- {"sst25vf064c"},{"sst25wf512"}, {"sst25wf010"}, {"sst25wf020"},
- {"sst25wf040"},
+ {"s25fl128s"}, {"s25fl129p0"}, {"s25fl129p1"}, {"s25sl004a"},
+ {"s25sl008a"}, {"s25sl016a"}, {"s25sl032a"}, {"s25sl064a"},
+ {"s25fl008k"}, {"s25fl016k"}, {"s25fl064k"}, {"s25fl132k"},
+ {"sst25vf040b"}, {"sst25vf080b"}, {"sst25vf016b"}, {"sst25vf032b"},
+ {"sst25vf064c"}, {"sst25wf512"}, {"sst25wf010"}, {"sst25wf020"},
+ {"sst25wf040"}, {"sst25wf080"},
{"m25p05"}, {"m25p10"}, {"m25p20"}, {"m25p40"},
{"m25p80"}, {"m25p16"}, {"m25p32"}, {"m25p64"},
- {"m25p128"}, {"n25q032"},
+ {"m25p128"},
{"m25p05-nonjedec"}, {"m25p10-nonjedec"}, {"m25p20-nonjedec"},
{"m25p40-nonjedec"}, {"m25p80-nonjedec"}, {"m25p16-nonjedec"},
{"m25p32-nonjedec"}, {"m25p64-nonjedec"}, {"m25p128-nonjedec"},
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index 7d0150d..22d977f 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -518,6 +518,19 @@ config MTD_NAND_XWAY
Enables support for NAND Flash chips on Lantiq XWAY SoCs. NAND is attached
to the External Bus Unit (EBU).
+config MTD_NAND_EP501X
+ tristate "Driver for Eureka EP501/EP501G1/EP501G3 Controllers"
+ depends on MTD_NAND
+ help
+ Enables NAND flash support for the Eureka EP501, EP501G1
+ and EP501G3 controllers.
+
+config MTD_NAND_EP501X_UBOOTENV
+ tristate "U-Boot Environment Access for LSI's APP and ACP"
+ depends on ( MTD_NAND_EP501X && CRC32 )
+ help
+ Add U-Boot environment access on LSI's APP/ACP boards.
+
config MTD_NAND_SUNXI
tristate "Support for NAND on Allwinner SoCs"
depends on ARCH_SUNXI
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index bd38f21..d0f269f 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -50,6 +50,8 @@ obj-$(CONFIG_MTD_NAND_JZ4740) += jz4740_nand.o
obj-$(CONFIG_MTD_NAND_GPMI_NAND) += gpmi-nand/
obj-$(CONFIG_MTD_NAND_XWAY) += xway_nand.o
obj-$(CONFIG_MTD_NAND_BCM47XXNFLASH) += bcm47xxnflash/
+obj-$(CONFIG_MTD_NAND_EP501X) += lsi_acp_nand.o
+obj-$(CONFIG_MTD_NAND_EP501X_UBOOTENV) += lsi_ubootenv.o
obj-$(CONFIG_MTD_NAND_SUNXI) += sunxi_nand.o
nand-objs := nand_base.o nand_bbt.o nand_timings.o
diff --git a/drivers/mtd/nand/lsi_acp_nand.c b/drivers/mtd/nand/lsi_acp_nand.c
new file mode 100644
index 0000000..cdc0694
--- /dev/null
+++ b/drivers/mtd/nand/lsi_acp_nand.c
@@ -0,0 +1,3678 @@
+/*
+ * drivers/lsi/acp/nand.c
+ *
+ * NAND Controller Driver for LSI's ACP
+ *
+ * Copyright (C) 2009 LSI Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#include <linux/slab.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/spinlock.h>
+#include <linux/delay.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/partitions.h>
+#include <linux/of.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <asm/cacheflush.h>
+
+/* -- DEBUG --------------------------------------------------------- */
+
+#include <asm/lsi/debug.h>
+
+/* -- LOGIO --------------------------------------------------------- */
+
+#undef LOGIO
+/*#define LOGIO*/
+#ifdef LOGIO
+int enable_logio;
+static inline unsigned long _READL(const char *, int, unsigned long);
+static inline unsigned long
+_READL(const char *file, int line, unsigned long address)
+{
+ unsigned long value;
+
+ value = readl(address);
+
+ if (0 != enable_logio)
+ pr_info("%s:%d - Read 0x%08lx from 0x%08lx\n",
+ file, line, value, address);
+
+ return value;
+}
+#define READL(address) _READL(__FILE__, __LINE__, (address))
+static inline void _WRITEL(const char *, int, unsigned long, unsigned long);
+static inline void
+_WRITEL(const char *file, int line, unsigned long value, unsigned long address)
+{
+ writel(value, address);
+
+ if (0 != enable_logio)
+ pr_err("%s:%d - Wrote 0x%08lx to 0x%08lx\n",
+ file, line, value, address);
+}
+#define WRITEL(value, address) _WRITEL(__FILE__, __LINE__, (value), (address))
+#else /* LOGIO */
+#define READL(address) readl((address))
+#define WRITEL(value, address) writel((value), (address))
+#endif /* LOGIO */
+
+/*
+ ----------------------------------------------------------------------
+*/
+
+#define NAND_DATA_REG 0x00000000
+#define NAND_CMD_REG 0x00008000
+#define NAND_INDEX_REG 0x00008004
+#define NAND_STATUS1_REG 0x00008008
+#define NAND_STATUS2_REG 0x0000800C
+#define NAND_ID0_REG 0x00008010
+#define NAND_ID1_REG 0x00008014
+#define NAND_ID2_REG 0x00008018
+#define NAND_ID3_REG 0x0000801C
+#define NAND_ID4_REG 0x00008020
+#define NAND_ID5_REG 0x00008024
+#define NAND_ID6_REG 0x00008028
+#define NAND_ID7_REG 0x0000802C
+#define NAND_INTR_EN_REG 0x00008030
+#define NAND_INTR_STATUS_REG 0x00008034
+#define NAND_INTR_REG 0x00008038
+#define NAND_ECC_ADDR_LOG_REG 0x0000803C
+#define NAND_ECC_VAL_REG 0x00008040
+#define NAND_ECC_INJECT_REG 0x00008044
+#define NAND_EXT_INDEX_REG 0x00008048
+#define NAND_TIMING1_REG 0x0000804C
+#define NAND_TIMING2_REG 0x00008050
+#define NAND_CONFIG_REG 0x00008054
+#define NAND_PECC_REG 0x00008058
+
+#define EP501_NAND_DATA_REG 0x0000
+#define EP501_NAND_CMD_REG 0x8000
+#define EP501_NAND_INDEX_REG 0x8004
+#define EP501_NAND_STATUS0_REG 0x8008
+#define EP501_NAND_STATUS1_REG 0x800C
+#define EP501_NAND_ID0_REG 0x8010
+#define EP501_NAND_ID1_REG 0x8014
+#define EP501_NAND_ID2_REG 0x8018
+#define EP501_NAND_ID3_REG 0x801C
+#define EP501_NAND_ID4_REG 0x8020
+#define EP501_NAND_ID5_REG 0x8024
+#define EP501_NAND_ID6_REG 0x8028
+#define EP501_NAND_ID7_REG 0x802C
+#define EP501_NAND_INTR_EN_REG 0x8030
+#define EP501_NAND_INTR_STATUS_REG 0x8034
+#define EP501_NAND_INTR_REG 0x8038
+#define EP501_NAND_ECC_ADDR_LOG_REG 0x803C
+#define EP501_NAND_ECC_VAL_REG 0x8040
+#define EP501_NAND_ECC_INJECT_REG 0x8044
+#define EP501_NAND_EXT_INDEX_REG 0x8048
+#define EP501_NAND_TIMING0_REG 0x804C
+#define EP501_NAND_TIMING1_REG 0x8050
+#define EP501_NAND_CONFIG_REG 0x8054
+#define EP501_NAND_PECC_REG 0x8058
+
+#define EP501G1_NAND_DATA_REG 0x0000
+#define EP501G1_NAND_CMD_REG 0x8000
+#define EP501G1_NAND_INDEX_REG 0x8004
+#define EP501G1_NAND_STATUS0_REG 0x8008
+#define EP501G1_NAND_ID0_REG 0x8010
+#define EP501G1_NAND_ID2_REG 0x8018
+#define EP501G1_NAND_ID4_REG 0x8020
+#define EP501G1_NAND_ID6_REG 0x8028
+#define EP501G1_NAND_INTR_EN_REG 0x8030
+#define EP501G1_NAND_INTR_STATUS_REG 0x8034
+#define EP501G1_NAND_INTR_REG 0x8038
+#define EP501G1_NAND_EXT_INDEX_REG 0x8048
+#define EP501G1_NAND_TIMING0_REG 0x804C
+#define EP501G1_NAND_TIMING1_REG 0x8050
+#define EP501G1_NAND_CONFIG_REG 0x8054
+#define EP501G1_NAND_1BIT_ECC0_STATUS 0x8058
+#define EP501G1_NAND_1BIT_ECC1_STATUS 0x805c
+#define EP501G1_NAND_1BIT_ECC2_STATUS 0x8060
+#define EP501G1_NAND_1BIT_ECC3_STATUS 0x8064
+#define EP501G1_NAND_1BIT_ECC4_STATUS 0x8068
+#define EP501G1_NAND_1BIT_ECC5_STATUS 0x806c
+#define EP501G1_NAND_1BIT_ECC6_STATUS 0x8070
+#define EP501G1_NAND_1BIT_ECC7_STATUS 0x8074
+#define EP501G1_NAND_BCH_STATUS 0x807c
+#define EP501G1_NAND_SYN_R12_S0 0x8080
+#define EP501G1_NAND_SYN_R34_S0 0x8084
+#define EP501G1_NAND_SYN_R56_S0 0x8088
+#define EP501G1_NAND_SYN_R78_S0 0x808c
+#define EP501G1_NAND_SYN_R12_S1 0x8090
+#define EP501G1_NAND_SYN_R34_S1 0x8094
+#define EP501G1_NAND_SYN_R56_S1 0x8098
+#define EP501G1_NAND_SYN_R78_S1 0x809c
+#define EP501G1_NAND_SYN_R12_S2 0x80a0
+#define EP501G1_NAND_SYN_R34_S2 0x80a4
+#define EP501G1_NAND_SYN_R56_S2 0x80a8
+#define EP501G1_NAND_SYN_R78_S2 0x80ac
+#define EP501G1_NAND_SYN_R12_S3 0x80b0
+#define EP501G1_NAND_SYN_R34_S3 0x80b4
+#define EP501G1_NAND_SYN_R56_S3 0x80b8
+#define EP501G1_NAND_SYN_R78_S3 0x80bc
+#define EP501G1_NAND_SYN_R12_S4 0x80c0
+#define EP501G1_NAND_SYN_R34_S4 0x80c4
+#define EP501G1_NAND_SYN_R56_S4 0x80c8
+#define EP501G1_NAND_SYN_R78_S4 0x80cc
+#define EP501G1_NAND_SYN_R12_S5 0x80d0
+#define EP501G1_NAND_SYN_R34_S5 0x80d4
+#define EP501G1_NAND_SYN_R56_S5 0x80d8
+#define EP501G1_NAND_SYN_R78_S5 0x80dc
+#define EP501G1_NAND_SYN_R12_S6 0x80e0
+#define EP501G1_NAND_SYN_R34_S6 0x80e4
+#define EP501G1_NAND_SYN_R56_S6 0x80e8
+#define EP501G1_NAND_SYN_R78_S6 0x80ec
+#define EP501G1_NAND_SYN_R12_S7 0x80f0
+#define EP501G1_NAND_SYN_R34_S7 0x80f4
+#define EP501G1_NAND_SYN_R56_S7 0x80f8
+#define EP501G1_NAND_SYN_R78_S7 0x80fc
+
+#define EP501G3_NAND_DATA_REG 0x0000
+#define EP501G3_NAND_CMD_REG 0x8000
+#define EP501G3_NAND_INDEX_REG 0x8004
+#define EP501G3_NAND_STATUS0_REG 0x8008
+#define EP501G3_NAND_ID0_REG 0x8010
+#define EP501G3_NAND_ID2_REG 0x8018
+#define EP501G3_NAND_ID4_REG 0x8020
+#define EP501G3_NAND_ID6_REG 0x8028
+#define EP501G3_NAND_INTR_EN_REG 0x8030
+#define EP501G3_NAND_INTR_STATUS_REG 0x8034
+#define EP501G3_NAND_INTR_REG 0x8038
+#define EP501G3_NAND_EXT_INDEX_REG 0x8048
+#define EP501G3_NAND_TIMING0_REG 0x804C
+#define EP501G3_NAND_TIMING1_REG 0x8050
+#define EP501G3_NAND_CONFIG_REG 0x8054
+#define EP501G3_NAND_TIMING2_REG 0x805c
+#define EP501G3_NAND_BCH_STATUS 0x807c
+#define EP501G3_NAND_SYN_R12_S0 0x8080
+#define EP501G3_NAND_SYN_R34_S0 0x8084
+#define EP501G3_NAND_SYN_R56_S0 0x8088
+#define EP501G3_NAND_SYN_R78_S0 0x808c
+#define EP501G3_NAND_SYN_R12_S1 0x8090
+#define EP501G3_NAND_SYN_R34_S1 0x8094
+#define EP501G3_NAND_SYN_R56_S1 0x8098
+#define EP501G3_NAND_SYN_R78_S1 0x809c
+#define EP501G3_NAND_SYN_R12_S2 0x80a0
+#define EP501G3_NAND_SYN_R34_S2 0x80a4
+#define EP501G3_NAND_SYN_R56_S2 0x80a8
+#define EP501G3_NAND_SYN_R78_S2 0x80ac
+#define EP501G3_NAND_SYN_R12_S3 0x80b0
+#define EP501G3_NAND_SYN_R34_S3 0x80b4
+#define EP501G3_NAND_SYN_R56_S3 0x80b8
+#define EP501G3_NAND_SYN_R78_S3 0x80bc
+#define EP501G3_NAND_SYN_R12_S4 0x80c0
+#define EP501G3_NAND_SYN_R34_S4 0x80c4
+#define EP501G3_NAND_SYN_R56_S4 0x80c8
+#define EP501G3_NAND_SYN_R78_S4 0x80cc
+#define EP501G3_NAND_SYN_R12_S5 0x80d0
+#define EP501G3_NAND_SYN_R34_S5 0x80d4
+#define EP501G3_NAND_SYN_R56_S5 0x80d8
+#define EP501G3_NAND_SYN_R78_S5 0x80dc
+#define EP501G3_NAND_SYN_R12_S6 0x80e0
+#define EP501G3_NAND_SYN_R34_S6 0x80e4
+#define EP501G3_NAND_SYN_R56_S6 0x80e8
+#define EP501G3_NAND_SYN_R78_S6 0x80ec
+#define EP501G3_NAND_SYN_R12_S7 0x80f0
+#define EP501G3_NAND_SYN_R34_S7 0x80f4
+#define EP501G3_NAND_SYN_R56_S7 0x80f8
+#define EP501G3_NAND_SYN_R78_S7 0x80fc
+#define EP501G3_NAND_SYN_R12_S8 0x8100
+#define EP501G3_NAND_SYN_R34_S8 0x8104
+#define EP501G3_NAND_SYN_R56_S8 0x8108
+#define EP501G3_NAND_SYN_R78_S8 0x810c
+#define EP501G3_NAND_SYN_R12_S9 0x8110
+#define EP501G3_NAND_SYN_R34_S9 0x8114
+#define EP501G3_NAND_SYN_R56_S9 0x8118
+#define EP501G3_NAND_SYN_R78_S9 0x811c
+#define EP501G3_NAND_SYN_R12_S10 0x8120
+#define EP501G3_NAND_SYN_R34_S10 0x8124
+#define EP501G3_NAND_SYN_R56_S10 0x8128
+#define EP501G3_NAND_SYN_R78_S10 0x812c
+#define EP501G3_NAND_SYN_R12_S11 0x8130
+#define EP501G3_NAND_SYN_R34_S11 0x8134
+#define EP501G3_NAND_SYN_R56_S11 0x8138
+#define EP501G3_NAND_SYN_R78_S11 0x813c
+#define EP501G3_NAND_SYN_R12_S12 0x8140
+#define EP501G3_NAND_SYN_R34_S12 0x8144
+#define EP501G3_NAND_SYN_R56_S12 0x8148
+#define EP501G3_NAND_SYN_R78_S12 0x814c
+#define EP501G3_NAND_SYN_R12_S13 0x8150
+#define EP501G3_NAND_SYN_R34_S13 0x8154
+#define EP501G3_NAND_SYN_R56_S13 0x8158
+#define EP501G3_NAND_SYN_R78_S13 0x815c
+#define EP501G3_NAND_SYN_R12_S14 0x8160
+#define EP501G3_NAND_SYN_R34_S14 0x8164
+#define EP501G3_NAND_SYN_R56_S14 0x8168
+#define EP501G3_NAND_SYN_R78_S14 0x816c
+#define EP501G3_NAND_SYN_R12_S15 0x8170
+#define EP501G3_NAND_SYN_R34_S15 0x8174
+#define EP501G3_NAND_SYN_R56_S15 0x8178
+#define EP501G3_NAND_SYN_R78_S15 0x817c
+
+/*
+ ==============================================================================
+ ==============================================================================
+ Some Oddities...
+
+ -1-
+ Reading EP501 registers while the device is calculating ECC will
+ hang the AHB. As the only way to know that an ECC calculation is in
+ progress is to read the "extra bits" added to the interrupt status
+ register, this can cause problems. To get around this, the
+ PECC_BUSY signal from the controller is also available in a general
+ purpose system register. 0x149.0.0xc/0x0020_0040_0000_c00c, bit 24.
+ So, before reading the interrupt status register (or any other
+ register for that matter) make sure the bit mentioned above is
+ clear. See BZ21212.
+
+ -2-
+ Extra bits have been added to the interrupt status register. See
+ BZ21196. From that defect...
+
+ == Bit 0
+ This bit is set when un-correctable ECC is detected. This bit can be
+ cleared by writing "0" to this register. Writing "1" has no
+ effect. An interrupt is generated if this bit and the enable bit
+ (bit 0) in the Interrupt Enable Register are "1". This bit is not
+ set if ECC is disabled.
+
+ == Bit 1
+ This bit is set when correctable ECC is detected. This bit can be
+ cleared by writing "0" to this register. Writing "1" has no
+ effect. An interrupt is generated if this bit and the enable bit
+ (bit 1) in the Interrupt Enable Register are "1". This bit is not
+ set if ECC is disabled.
+
+ == Bit 2
+ This bit is set when a rising edge is detected on the non gated
+ READY/BUSY# input from the NAND Flash. This bit can be cleared by
+ writing a "0" to this register. Writing a "1" has no effect. An
+ interrupt is generated if this bit and the enable bit (bit 2) in the
+ Interrupt Enable Register are "1".
+
+ == Bit 3
+ This bit is set when a falling edge is detected on the non gated
+ READY/BUSY# input from the NAND Flash. This bit can be cleared by
+ writing a "0" to this register. Writing a "1" has no effect. An
+ interrupt is generated if this bit and the enable bit (bit 3) in the
+ Interrupt Enable Register are "1".
+
+ == Bit 4
+ This bit is set when a falling edge is detected on the PECC_BUSY
+ signal which indicates when the NAND controller has taken control of
+ the NAND Flash for ECC byte access. This bit can be cleared by
+ writing a "0" to this register. Writing a "1" has no effect. An
+ interrupt is generated if this bit and the enable bit (bit 4) in the
+ Interrupt Enable Register are "1".
+
+ == Bit 5
+ This bit is read only and is the synchronized level on the non gated
+ READY/BUSY# input from the NAND Flash. This bit can be used to poll
+ the status of this signal and is not used to generate an interrupt.
+
+ == Bit 6
+ This bit is read only and indicates the level on the PECC_BUSY
+ signal which indicates when the NAND controller has taken control of
+ the NAND Flash for ECC byte access. This bit can be used to poll the
+ level of this signal and is not used to generate an interrupt.
+
+ ==============================================================================
+ ==============================================================================
+*/
+
+static void *gpreg_base;
+static void *pecc_busy_register;
+static unsigned long pecc_busy_mask;
+
+#define MAX_READ_BUF 16
+
+/*
+ ----------------------------------------------------------------------
+ MTD structures
+*/
+
+static struct mtd_info lsi_nand_mtd = { 0 };
+static struct nand_chip lsi_nand_chip = { 0 };
+
+static struct lsi_nand_private {
+ int cur; /* -1 means there is no meaningful data in buffer */
+ uint8_t buf[MAX_READ_BUF];
+} lsi_nand_private;
+
+#define NAND_CMD_START_ECC_READ 0x23
+
+#define NAND_CMD_CE_OFF_501 0xEE
+#define NAND_CMD_CE_OFF_501G1 0xEE
+#define NAND_CMD_CE_OFF_501G3 0xFE
+static int nand_cmd_ce_off;
+
+typedef union {
+ unsigned long raw;
+
+ struct {
+#ifdef CONFIG_ACP
+ unsigned long th:8;
+ unsigned long trp:8;
+ unsigned long twp:8;
+ unsigned long ts:8;
+#else
+ unsigned long ts:8;
+ unsigned long twp:8;
+ unsigned long trp:8;
+ unsigned long th:8;
+#endif
+ } __packed bits;
+} nand_timing_control_register_0_t;
+
+typedef union {
+ unsigned long raw;
+
+ struct {
+#ifdef CONFIG_ACP
+ unsigned long twb:8;
+ unsigned long trr:8;
+ unsigned long trh:8;
+ unsigned long twh:8;
+#else
+ unsigned long twh:8;
+ unsigned long trh:8;
+ unsigned long trr:8;
+ unsigned long twb:8;
+#endif
+ } __packed bits;
+} __packed nand_timing_control_register_1_t;
+
+typedef union {
+ unsigned long raw;
+
+ struct {
+#ifdef CONFIG_ACP
+ unsigned long:8;
+ unsigned long trhw:8;
+ unsigned long twhr:8;
+ unsigned long tccs:8;
+#else
+ unsigned long tccs:8;
+ unsigned long twhr:8;
+ unsigned long trhw:8;
+ unsigned long:8;
+#endif
+ } __packed bits;
+} __packed nand_timing_control_register_2_t;
+
+typedef enum {
+ LSI_NAND_NONE, LSI_NAND_EP501, LSI_NAND_EP501G1, LSI_NAND_EP501G3
+} lsi_nand_type_t;
+
+static lsi_nand_type_t lsi_nand_type;
+
+typedef struct page_wise_ecc_status_st {
+ unsigned err_bit:3;
+ unsigned column:9;
+ unsigned status:2;
+ unsigned rsvd:18;
+} page_wise_ecc_status_t;
+
+/*
+ =============================================================================
+ =============================================================================
+ Concerning ECC
+
+ The EP501 only supports 1 bit ECC mode. The EP501G1 supports both 1
+ bit and 4 bit modes. The EP501G3 supports 4 bit, 8 bit, and 12 bit.
+ The NAND part normally used on ACP boards has 2K pages (supported by
+ all three controllers) with 64 bytes of OOB. For a 2K page, 1 bit
+ ECC uses 12 bytes, 4 bit ECC uses 32 bytes, 8 bit ECC uses 64 bytes
+ and 12 bit ECC uses 80 bytes. In order to to keep the bad block
+ markers (first two bytes) and leave some OOB available for file
+ systems etc., this driver only supports 1 bit ECC or 4 bit ECC.
+
+ For now, the EP501 version will use 1 bit ECC (only option), the
+ EP501G1 version will use 4 bit (for compabitility with the EP501G3)
+ and teh EP501G3 versions will use 4 bit (due to the amount of OOB
+ required and for compatibility with the EP501G1).
+
+ EP501
+
+ The driver has not been tested with small page (512 byte) devices.
+ The only usable option is 2K. So, the OOB should be 64 bytes. The
+ first 2 bytes are reserved for marking bad blocks. The last 12
+ bytes are reserved for ECC. All other bytes are free. See
+ lsi_ep501_2k_ecclayout below.
+
+ EP501G1
+
+ This driver has been tested with 2K and 4K page sizes using 1 bit
+ and 4 bit ECC.
+ =============================================================================
+ =============================================================================
+*/
+
+static struct nand_ecclayout lsi_2k_1bit_ecclayout = {
+ .eccbytes = 12,
+ .eccpos = {
+ 52, 53, 54, 55, 56, 57,
+ 58, 59, 60, 61, 62, 63},
+ .oobfree = {{2, 50} }
+};
+
+/*
+static struct nand_ecclayout lsi_4k_1bit_ecclayout = {
+ .eccbytes = 24,
+ .eccpos = {
+ 52, 53, 54, 55, 56, 57,
+ 58, 59, 60, 61, 62, 63},
+ .oobfree = {{2, 50}}
+};
+*/
+
+static struct nand_ecclayout lsi_2k_4bit_ecclayout = {
+ .eccbytes = 32,
+ .eccpos = {
+ 32, 33, 34, 35, 36, 37, 38, 39,
+ 40, 41, 42, 43, 44, 45, 46, 47,
+ 48, 49, 50, 51, 52, 53, 54, 55,
+ 56, 57, 58, 59, 60, 61, 62, 63 },
+ .oobfree = {{2, 30} }
+};
+
+static struct nand_ecclayout lsi_4k_4bit_ecclayout = {
+ .eccbytes = 64,
+ .eccpos = {
+ 64, 65, 66, 67, 68, 69, 70, 71,
+ 72, 73, 74, 75, 76, 77, 78, 79,
+ 80, 81, 82, 83, 84, 85, 86, 87,
+ 88, 89, 90, 91, 92, 93, 94, 95,
+ 96, 97, 98, 99, 100, 101, 102, 103,
+ 104, 105, 106, 107, 108, 109, 110, 111,
+ 112, 113, 114, 115, 116, 117, 118, 119,
+ 120, 121, 122, 123, 124, 125, 126, 127
+ },
+ .oobfree = {{2, 63} }
+};
+
+#ifdef NOT_USED
+
+static struct nand_ecclayout lsi_8k_4bit_ecclayout = {
+ .eccbytes = 128,
+ .eccpos = {
+ 128, 129, 130, 131, 132, 133, 134, 135,
+ 136, 137, 138, 139, 140, 141, 142, 143,
+ 144, 145, 146, 147, 148, 149, 150, 151,
+ 152, 153, 154, 155, 156, 157, 158, 159,
+ 160, 161, 162, 163, 164, 165, 166, 167,
+ 168, 169, 170, 171, 172, 173, 174, 175,
+ 176, 177, 178, 179, 180, 181, 182, 183,
+ 184, 185, 186, 187, 188, 189, 190, 191,
+ 192, 193, 194, 195, 196, 197, 198, 199,
+ 200, 201, 202, 203, 204, 205, 206, 207,
+ 208, 209, 210, 211, 212, 213, 214, 215,
+ 216, 217, 218, 219, 220, 221, 222, 223,
+ 224, 225, 226, 227, 228, 229, 230, 231,
+ 232, 233, 234, 235, 236, 237, 238, 239,
+ 240, 241, 242, 243, 244, 245, 246, 247,
+ 248, 249, 250, 251, 252, 253, 254, 255
+ },
+ .oobfree = {{2, 126} }
+};
+
+#endif
+
+/*
+ -----------------------------------------------------------------------------
+ lsi_nand_hwcontrol
+*/
+
+static void
+lsi_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
+{
+ struct nand_chip *chip = mtd->priv;
+
+ if (cmd != NAND_CMD_NONE)
+ WRITEL(cmd, (chip->IO_ADDR_W + NAND_CMD_REG));
+}
+
+/*
+ ------------------------------------------------------------------------------
+ lsi_nand_device_ready
+
+ The READ/BUSY# input from the NAND device(s) (ORed if there are more
+ than one) is availble as an extra bit in the interrupt status
+ register. Note that this register shouldn't be read unless the
+ controller is not in the middle of calculating ECC (see "Some
+ Oddities..." above).
+*/
+
+static int
+lsi_nand_device_ready(struct mtd_info *mtd)
+{
+ struct nand_chip *chip = mtd->priv;
+ unsigned long interrupt_status;
+
+ /* Get the status. */
+ interrupt_status = READL(chip->IO_ADDR_R + NAND_INTR_STATUS_REG);
+
+ return interrupt_status & NAND_STATUS_TRUE_READY;
+}
+
+/**
+ * lsi_nand_command - [DEFAULT] Send command to NAND large page device
+ * @mtd: MTD device structure
+ * @command: the command to be sent
+ * @column: the column address for this command, -1 if none
+ * @page_addr: the page address for this command, -1 if none
+ *
+ * Send command to NAND device. This is the version for the new large page
+ * devices We dont have the separate regions as we have in the small page
+ * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
+ */
+static void
+lsi_nand_command(struct mtd_info *mtd, unsigned int command,
+ int column, int page_addr)
+{
+ register struct nand_chip *chip = mtd->priv;
+ unsigned int status = 0;
+ struct lsi_nand_private *priv = &lsi_nand_private;
+ struct device_node *np = NULL;
+
+ DEBUG_PRINT("command=0x%x\n", command);
+ command &= 0xff;
+
+ /* Emulate NAND_CMD_READOOB */
+ if (command == NAND_CMD_READOOB) {
+ column += mtd->writesize;
+ command = NAND_CMD_READ0;
+ }
+
+ /* return if unhandled command is issued */
+ if (command != NAND_CMD_READ0 &&
+ command != NAND_CMD_SEQIN &&
+ command != NAND_CMD_ERASE1 &&
+ command != NAND_CMD_STATUS &&
+ command != NAND_CMD_READID &&
+ command != NAND_CMD_RESET &&
+ command != NAND_CMD_START_ECC_READ &&
+ command != NAND_CMD_PAGEPROG &&
+ command != NAND_CMD_ERASE2) {
+ pr_err("lsi_nand_command(): WARN: Unhandled command 0x%x "
+ "issued for page=0x%x, column=0x%x.\n",
+ command, page_addr, column);
+ return;
+ }
+
+ priv->cur = -1;
+ /* Command latch cycle */
+ chip->cmd_ctrl(mtd, command,
+ NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
+
+ if (column != -1 || page_addr != -1) {
+ unsigned long index = 0;
+ unsigned long extended_index = 0;
+
+ /* column number */
+ /*
+ Since the ACP uses 8 bit device access, only that
+ mode is supported.
+ */
+
+ if (LSI_NAND_EP501 == lsi_nand_type) {
+ /* column number */
+ if (column != -1)
+ index = column & 0xfff;
+
+ /* page and block number */
+ if (page_addr != -1)
+ index += ((page_addr & 0x7ffff) << 12);
+ } else {
+ /* column number */
+ if (-1 != column) {
+ switch (mtd->writesize) {
+ case 512:
+ index |= (column & 0x1ff);
+ break;
+ case 2048:
+ index |= (column & 0xfff);
+ break;
+ case 4096:
+ index |= (column & 0x1fff);
+ break;
+ default:
+ break;
+ }
+ }
+
+ /* page_addr and block number */
+ if (-1 != page_addr) {
+ switch (mtd->writesize) {
+ case 512:
+ index |= (page_addr & 0x7fffff) << 9;
+ break;
+ case 2048:
+ index |= (page_addr & 0xfffff) << 12;
+ extended_index |=
+ (page_addr & 0xfff00000);
+ break;
+ case 4096:
+ index |= (page_addr & 0x7ffff) << 13;
+ extended_index |=
+ (page_addr & 0xfff80000);
+ break;
+ default:
+ break;
+ }
+ }
+ }
+
+ /* write index reg */
+ WRITEL(index, chip->IO_ADDR_W + NAND_INDEX_REG);
+
+ /* write ext index reg */
+ WRITEL(extended_index, chip->IO_ADDR_W + NAND_EXT_INDEX_REG);
+
+ /* Memory Barrier */
+ mb();
+ }
+
+ /* for read command, send 0xe0 so data is populated */
+ if (command == NAND_CMD_READ0) {
+ chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
+ NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
+ do {
+ udelay(chip->chip_delay);
+ status = READL((void *)pecc_busy_register);
+ } while (0 != (status & pecc_busy_mask));
+
+ /* wait until CHIP_BUSY goes low */
+ do {
+ udelay(chip->chip_delay);
+ status = chip->dev_ready(mtd);
+ } while (!status);
+ } else if (command == NAND_CMD_STATUS) {
+ udelay(chip->chip_delay);
+ priv->cur = 0;
+ priv->buf[0] = readb(chip->IO_ADDR_R + NAND_STATUS1_REG);
+ } else if (command == NAND_CMD_READID) {
+ priv->cur = 0;
+ priv->buf[0] = readb(chip->IO_ADDR_R + NAND_ID0_REG);
+ priv->buf[1] = readb(chip->IO_ADDR_R + NAND_ID2_REG);
+ priv->buf[2] = readb(chip->IO_ADDR_R + NAND_ID4_REG);
+ priv->buf[3] = readb(chip->IO_ADDR_R + NAND_ID6_REG);
+ }
+}
+
+/**
+ * lsi_nand_read_buf - [DEFAULT] read chip data into buffer
+ * @mtd: MTD device structure
+ * @buf: buffer to store date
+ * @len: number of bytes to read
+ *
+ * Default read function for 8bit buswith
+ */
+static void lsi_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
+{
+ int i = 0;
+ struct nand_chip *chip = (struct nand_chip *) mtd->priv;
+ uint32_t *p = (uint32_t *)buf;
+
+#if defined(LOGIO)
+ if (0 != enable_logio)
+ pr_notice("Reading NAND Buffer (len=%d)...\n", len);
+#endif
+
+ for (i = 0; i < (len >> 2); i++)
+ p[i] = readl(chip->IO_ADDR_R);
+}
+
+/**
+ * lsi_nand_write_buf - [DEFAULT] write buffer to chip
+ * @mtd: MTD device structure
+ * @buf: data buffer
+ * @len: number of bytes to write
+ *
+ * Default write function for 8bit buswith
+ */
+static void
+lsi_nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
+{
+ int i = 0;
+ struct nand_chip *chip = mtd->priv;
+ uint32_t *p = (uint32_t *)buf;
+
+#if defined(LOGIO)
+ if (0 != enable_logio)
+ pr_notice("Writing NAND Buffer (len=%d)...\n", len);
+#endif
+
+ for (i = 0; i < (len >> 2); i++)
+ writel(p[i], chip->IO_ADDR_W);
+}
+
+static int lsi_nand_read_status(struct mtd_info *mtd)
+{
+ struct nand_chip *chip = mtd->priv;
+
+ chip->cmd_ctrl(mtd, NAND_CMD_STATUS, 0);
+
+ return READL(chip->IO_ADDR_R + NAND_STATUS1_REG) & 0xff;
+}
+
+
+/**
+ * lsi_nand_wait - [DEFAULT] wait until the command is done
+ * @mtd: MTD device structure
+ * @chip: NAND chip structure
+ *
+ * Wait for command done. This applies to erase and program only
+ * Erase can take up to 400ms and program up to 20ms according to
+ * general NAND and SmartMedia specs
+ */
+static int lsi_nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
+{
+ unsigned long status = 0;
+ loff_t offset = 0;
+ struct device_node *np = NULL;
+
+ /*
+ When reading or writing, wait for the
+ controller's PECC_BUSY signal to clear.
+ */
+#ifdef NOT_USED
+ if (FL_READING == chip->state || FL_WRITING == chip->state) {
+ for (;;) {
+ status = READL((void *)pecc_busy_register);
+
+ if (0 == (status & pecc_busy_mask))
+ break;
+
+ udelay(chip->chip_delay);
+ }
+ }
+#else
+ for (;;) {
+ status = READL((void *)pecc_busy_register);
+
+ if (0 == (status & pecc_busy_mask))
+ break;
+
+ udelay(chip->chip_delay);
+ }
+#endif
+
+ /*
+ In all cases, wait for the NAND device to be "ready".
+
+ N.B. The FL_READING case is handled in lsi_nand_command().
+ */
+
+ if (FL_WRITING == chip->state || FL_ERASING == chip->state) {
+ for (;;) {
+ if (chip->dev_ready(mtd))
+ break;
+
+ udelay(chip->chip_delay);
+ }
+ }
+
+ /*
+ Then get the status.
+ */
+
+ for (;;) {
+ status = lsi_nand_read_status(mtd);
+
+ if (0 != (status & NAND_STATUS_READY))
+ break;
+
+ udelay(chip->chip_delay);
+ }
+
+ if (status & NAND_STATUS_FAIL) {
+ offset = (READL(chip->IO_ADDR_R + NAND_INDEX_REG) /
+ mtd->writesize) * mtd->writesize;
+ pr_err("lsi_nand_wait(): Action %d failed for "
+ "Offset: 0x%llx, status 0x%lx\n",
+ chip->state, offset, status);
+ }
+
+ return status;
+}
+
+/*
+ lsi_nand_ecc_hwctl
+*/
+
+void
+lsi_nand_ecc_hwctl(struct mtd_info *mtd, int mode)
+{
+ /* nothing to do to enable ECC */
+}
+
+/**
+ * lsi_nand_ecc_calculate
+ */
+
+int
+lsi_nand_ecc_calculate(struct mtd_info *mtd, const uint8_t *dat,
+ uint8_t *ecc_code)
+{
+ struct nand_chip *chip = mtd->priv;
+
+ /* start ECC calculation */
+ if (chip->state == FL_READING)
+ chip->cmdfunc(mtd, NAND_CMD_START_ECC_READ, -1, -1);
+ else if (chip->state == FL_WRITING)
+ chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
+
+ /* wait for PECC_BUSY to go down */
+ return chip->waitfunc(mtd, chip);
+}
+
+/**
+ * lsi_nand_ecc_correct
+ */
+
+int
+lsi_nand_ecc_correct(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc,
+ uint8_t *calc_ecc)
+{
+ /* nothing to do to correct ECC */
+ return 0;
+}
+
+/*
+ ------------------------------------------------------------------------------
+ report_ecc_errors_ep501
+*/
+
+static int
+report_ecc_errors_ep501(struct mtd_info *mtd, struct nand_chip *chip,
+ uint8_t *buffer, int page)
+{
+ int rc = 0;
+ unsigned long ecc_status;
+ page_wise_ecc_status_t *ecc_status_reg =
+ (page_wise_ecc_status_t *)&ecc_status;
+ int column;
+ int i;
+
+ for (i = 0; i < (mtd->writesize >> 9); i++) {
+ ecc_status = READL(chip->IO_ADDR_R + EP501_NAND_PECC_REG);
+ column = (i << 9) + ecc_status_reg->column;
+
+ if (1 == ecc_status_reg->status) {
+ pr_notice("Single ECC Error: "
+ "Page=0x%x Column=0x%x Bit=0x%x\n",
+ page, column, ecc_status_reg->err_bit);
+
+ if (column < mtd->writesize) {
+ buffer[column] ^=
+ (1 << ecc_status_reg->err_bit);
+ ++mtd->ecc_stats.corrected;
+ } else {
+ pr_err("Single ECC Error Not Corrected: "
+ "Column 0x%x not in "
+ "Page Size 0x%x\n",
+ column, mtd->writesize);
+ rc = -1;
+ }
+ } else if ((ecc_status & 0x3000) == 2) {
+ pr_err("Uncorrectable ECC Error: "
+ "Page=0x%x Column=0x%x\n",
+ page, column);
+ rc = -1;
+ }
+ }
+
+ return rc;
+}
+
+int i_to_a[8192] = {
+ -1, 0, 1, 7953, 2, 7715, 7954, 3551, 3, 3313, 7716, 5441,
+ 7955, 1529, 3552, 7477, 4, 7239, 3314, 1441, 7717, 7102, 5442,
+ 1291, 7956, 7545, 1530, 3075, 3553, 5203, 7478, 2784, 5, 2546,
+ 7240, 5080, 3315, 4596, 1442, 4965, 7718, 466, 7103, 7307,
+ 5443, 2837, 1292, 822, 7957, 801, 7546, 7001, 1531, 1203,
+ 3076, 4294, 3554, 1053, 5204, 3033, 7479, 6073, 2785, 6864, 6,
+ 6626, 2547, 7658, 7241, 2691, 5081, 5835, 3316, 2893, 4597,
+ 815, 1443, 2795, 4966, 2905, 7719, 3058, 467, 563, 7104, 6763,
+ 7308, 1956, 5444, 4056, 2838, 838, 1293, 6335, 823, 965, 7958,
+ 3626, 802, 2308, 7547, 4842, 7002, 7279, 1532, 4727, 1204,
+ 2462, 3077, 8003, 4295, 4358, 3555, 584, 1054, 7877, 5205,
+ 2629, 3034, 2599, 7480, 4992, 6074, 228, 2786, 7069, 6865,
+ 6970, 7, 6732, 6627, 4178, 2548, 7845, 7659, 6831, 7242, 5051,
+ 2692, 4754, 5082, 8181, 5836, 5864, 3317, 1826, 2894, 346,
+ 4598, 7639, 816, 4352, 1444, 2361, 2796, 4313, 4967, 5263,
+ 2906, 2391, 7720, 6584, 3059, 3388, 468, 2070, 564, 7693,
+ 7105, 7041, 6764, 1387, 7309, 6882, 1957, 4604, 5445, 4120,
+ 4057, 1433, 2839, 883, 839, 7765, 1294, 7442, 6336, 4489, 824,
+ 2224, 966, 260, 7959, 5281, 3627, 6388, 803, 7420, 2309, 2970,
+ 7548, 5597, 4843, 4681, 7003, 4373, 7280, 2453, 1533, 2667,
+ 4728, 213, 1205, 7320, 2463, 2557, 3078, 34, 8004, 2655, 4296,
+ 577, 4359, 4017, 3556, 727, 585, 4795, 1055, 3138, 7878, 6097,
+ 5206, 440, 2630, 3818, 3035, 600, 2600, 7645, 7481, 4303,
+ 4993, 2820, 6075, 325, 229, 7021, 2787, 1718, 7070, 8147,
+ 6866, 2746, 6971, 6525, 8, 6287, 6733, 3363, 6628, 2882, 4179,
+ 2508, 2549, 6263, 7846, 1480, 7660, 7909, 6832, 4562, 7243,
+ 6013, 5052, 4065, 2693, 2582, 4755, 2138, 5083, 6783, 8182,
+ 6197, 5837, 5184, 5865, 87, 3318, 7602, 1827, 489, 2895, 4557,
+ 347, 7177, 4599, 5859, 7640, 2448, 817, 7472, 4353, 2900,
+ 1445, 7407, 2362, 5907, 2797, 2639, 4314, 362, 4968, 3697,
+ 5264, 202, 2907, 3580, 2392, 1752, 7721, 6899, 6585, 5043,
+ 3060, 6150, 3389, 1846, 469, 2732, 2071, 6180, 565, 1726,
+ 7694, 7182, 7106, 2215, 7042, 5823, 6765, 5568, 1388, 4135,
+ 7310, 3237, 6883, 5359, 1958, 4443, 4605, 1761, 5446, 3779,
+ 4121, 136, 4058, 1688, 1434, 339, 2840, 3670, 884, 7987, 840,
+ 2417, 7766, 352, 1295, 4024, 7443, 2429, 6337, 8166, 4490,
+ 7494, 825, 2319, 2225, 2611, 967, 2330, 261, 7082, 7960, 4389,
+ 5282, 6494, 3628, 3940, 6389, 7145, 804, 6593, 7421, 1411,
+ 2310, 4211, 2971, 7607, 7549, 5626, 5598, 1695, 4844, 283,
+ 4682, 7943, 7004, 6125, 4374, 4813, 7281, 4516, 2454, 7979,
+ 1534, 2153, 2668, 3174, 4729, 5507, 214, 5025, 1206, 4956,
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+ 1641, 2253, 709, 1869, 382, 8014, 1966, 3567, 1736, 7505,
+ 7934, 2758, 4230, 3191, 2086, 3336, 3244, 1085, 3300, 635,
+ 905, 1980, 7139, 1840, 2502, 2964, 6825, 5829, 3545, 2751,
+ 6063, 2276, 5534, 4042, 7346, 6304, 1560, 5588, 5808, 4193,
+ 394, 5784, 1628, 2517, 5212, 6807, 2001, 3218, 7354, 5656,
+ 2198, 1801, 6928, 5380, 3477, 1425, 1580, 5059, 7123, 4283,
+ 5405, 6976, 2851, 3352, 3161, 4737, 1065, 2439, 6536, 3900,
+ 2570, 2708, 6955, 5102, 501, 2042, 3887, 1153, 7734, 8033,
+ 5394, 2539, 6577, 7595, 2146, 67, 4264, 5309, 3746, 4339,
+ 7683, 7048, 180, 6530, 376, 3635, 2620, 2054, 5686, 3718, 856,
+ 4477, 1928, 6140, 6056, 8110, 1674, 1666, 446, 6448, 592,
+ 5113, 5147, 5651, 1080, 5646, 2534, 5333, 3910, 425, 777,
+ 6114, 1124, 5300, 8093
+};
+
+int a_to_i[8192] = {
+ 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 1455,
+ 2910, 5820, 2263, 4526, 1779, 3558, 7116, 4663, 449, 898,
+ 1796, 3592, 7184, 7567, 7857, 6349, 5173, 3525, 7050, 4795,
+ 217, 434, 868, 1736, 3472, 6944, 5103, 625, 1250, 2500, 5000,
+ 703, 1406, 2812, 5624, 3679, 7358, 7379, 7177, 7613, 7893,
+ 6149, 5541, 3813, 7626, 7739, 6617, 5661, 2453, 4906, 1019,
+ 2038, 4076, 8152, 6687, 4497, 1677, 3354, 6708, 4551, 1569,
+ 3138, 6276, 5287, 3297, 6594, 5675, 2553, 5106, 587, 1174,
+ 2348, 4696, 287, 574, 1148, 2296, 4592, 1615, 3230, 6460,
+ 6103, 2561, 5122, 3499, 6998, 4867, 937, 1874, 3748, 7496,
+ 7999, 7121, 4621, 437, 874, 1748, 3496, 6992, 4879, 945, 1890,
+ 3780, 7560, 7871, 6353, 5133, 3509, 7018, 4987, 857, 1714,
+ 3428, 6856, 4159, 1489, 2978, 5956, 2855, 5710, 2355, 4710,
+ 355, 710, 1420, 2840, 5680, 2511, 5022, 659, 1318, 2636, 5272,
+ 3231, 6462, 6099, 2569, 5138, 3467, 6934, 4995, 681, 1362,
+ 2724, 5448, 3903, 7806, 6483, 5897, 3005, 6010, 2907, 5814,
+ 2243, 4486, 1699, 3398, 6796, 4279, 1217, 2434, 4868, 935,
+ 1870, 3740, 7480, 8159, 6673, 4493, 1717, 3434, 6868, 4103,
+ 1441, 2882, 5764, 2215, 4430, 1843, 3686, 7372, 7223, 7617,
+ 7725, 6645, 5701, 2341, 4682, 315, 630, 1260, 2520, 5040, 719,
+ 1438, 2876, 5752, 2399, 4798, 211, 422, 844, 1688, 3376, 6752,
+ 4463, 1905, 3810, 7620, 7719, 6625, 5741, 2421, 4842, 123,
+ 246, 492, 984, 1968, 3936, 7872, 6191, 5617, 3661, 7322, 7323,
+ 7321, 7325, 7317, 7301, 7333, 7397, 7269, 7525, 8037, 7013,
+ 4965, 869, 1738, 3476, 6952, 5119, 593, 1186, 2372, 4744, 191,
+ 382, 764, 1528, 3056, 6112, 2671, 5342, 3091, 6182, 5603,
+ 3689, 7378, 7179, 7609, 7901, 6165, 5509, 3749, 7498, 7995,
+ 7129, 4637, 405, 810, 1620, 3240, 6480, 5903, 2993, 5986,
+ 2923, 5846, 2051, 4102, 1443, 2886, 5772, 2231, 4462, 1907,
+ 3814, 7628, 7735, 6593, 5677, 2549, 5098, 635, 1270, 2540,
+ 5080, 543, 1086, 2172, 4344, 1119, 2238, 4476, 1879, 3758,
+ 7516, 7959, 7041, 4781, 245, 490, 980, 1960, 3920, 7840, 6383,
+ 5233, 3405, 6810, 4251, 1177, 2354, 4708, 359, 718, 1436,
+ 2872, 5744, 2383, 4766, 147, 294, 588, 1176, 2352, 4704, 367,
+ 734, 1468, 2936, 5872, 2127, 4254, 1171, 2342, 4684, 311, 622,
+ 1244, 2488, 4976, 847, 1694, 3388, 6776, 4447, 1809, 3618,
+ 7236, 7463, 8161, 6765, 4469, 1861, 3722, 7444, 8071, 6817,
+ 4333, 1141, 2282, 4564, 1543, 3086, 6172, 5527, 3713, 7426,
+ 8107, 6905, 4189, 1301, 2602, 5204, 3335, 6670, 4531, 1737,
+ 3474, 6948, 5095, 609, 1218, 2436, 4872, 959, 1918, 3836,
+ 7672, 7775, 6417, 6029, 2741, 5482, 3963, 7926, 6211, 5417,
+ 4093, 8186, 6747, 4377, 1949, 3898, 7796, 6471, 5921, 3053,
+ 6106, 2587, 5174, 3523, 7046, 4771, 233, 466, 932, 1864, 3728,
+ 7456, 8175, 6769, 4429, 1845, 3690, 7380, 7175, 7585, 7917,
+ 6261, 5445, 3877, 7754, 6459, 6105, 2589, 5178, 3547, 7094,
+ 4803, 41, 82, 164, 328, 656, 1312, 2624, 5248, 3247, 6494,
+ 5907, 2953, 5906, 2955, 5910, 2947, 5894, 2979, 5958, 2851,
+ 5702, 2339, 4678, 291, 582, 1164, 2328, 4656, 463, 926, 1852,
+ 3704, 7408, 7247, 7473, 8141, 6709, 4549, 1573, 3146, 6292,
+ 5255, 3233, 6466, 5931, 3065, 6130, 2635, 5270, 3203, 6406,
+ 6051, 2793, 5586, 3595, 7190, 7555, 7849, 6397, 5205, 3333,
+ 6666, 4539, 1753, 3506, 7012, 4967, 865, 1730, 3460, 6920,
+ 5055, 721, 1442, 2884, 5768, 2239, 4478, 1875, 3750, 7500,
+ 7991, 7105, 4653, 501, 1002, 2004, 4008, 8016, 6927, 5041,
+ 717, 1434, 2868, 5736, 2431, 4862, 83, 166, 332, 664, 1328,
+ 2656, 5312, 3119, 6238, 5395, 3977, 7954, 7051, 4793, 221,
+ 442, 884, 1768, 3536, 7072, 4847, 113, 226, 452, 904, 1808,
+ 3616, 7232, 7471, 8177, 6733, 4405, 1989, 3978, 7956, 7047,
+ 4769, 237, 474, 948, 1896, 3792, 7584, 7919, 6257, 5453, 3893,
+ 7786, 6523, 5977, 2845, 5690, 2523, 5046, 707, 1414, 2828,
+ 5656, 2463, 4926, 979, 1958, 3916, 7832, 6303, 5265, 3213,
+ 6426, 6043, 2713, 5426, 4043, 8086, 6787, 4265, 1277, 2554,
+ 5108, 583, 1166, 2332, 4664, 479, 958, 1916, 3832, 7664, 7759,
+ 6449, 6093, 2613, 5226, 3451, 6902, 4163, 1321, 2642, 5284,
+ 3303, 6606, 5683, 2505, 5010, 651, 1302, 2604, 5208, 3359,
+ 6718, 4563, 1545, 3090, 6180, 5607, 3681, 7362, 7211, 7673,
+ 7773, 6421, 6021, 2725, 5450, 3899, 7798, 6467, 5929, 3069,
+ 6138, 2651, 5302, 3267, 6534, 5795, 2281, 4562, 1547, 3094,
+ 6188, 5623, 3649, 7298, 7339, 7417, 7261, 7445, 8069, 6821,
+ 4325, 1125, 2250, 4500, 1671, 3342, 6684, 4503, 1665, 3330,
+ 6660, 4519, 1761, 3522, 7044, 4775, 225, 450, 900, 1800, 3600,
+ 7200, 7663, 7793, 6477, 5941, 3013, 6026, 2747, 5494, 3907,
+ 7814, 6307, 5353, 3197, 6394, 5211, 3353, 6706, 4555, 1593,
+ 3186, 6372, 5223, 3425, 6850, 4139, 1529, 3058, 6116, 2663,
+ 5326, 3123, 6246, 5475, 3945, 7890, 6155, 5561, 3805, 7610,
+ 7899, 6169, 5533, 3733, 7466, 8187, 6745, 4381, 1941, 3882,
+ 7764, 6407, 6049, 2797, 5594, 3611, 7222, 7619, 7721, 6653,
+ 5717, 2309, 4618, 443, 886, 1772, 3544, 7088, 4815, 49, 98,
+ 196, 392, 784, 1568, 3136, 6272, 5295, 3313, 6626, 5739, 2425,
+ 4850, 75, 150, 300, 600, 1200, 2400, 4800, 47, 94, 188, 376,
+ 752, 1504, 3008, 6016, 2735, 5470, 3859, 7718, 6627, 5737,
+ 2429, 4858, 91, 182, 364, 728, 1456, 2912, 5824, 2095, 4190,
+ 1299, 2598, 5196, 3383, 6766, 4467, 1865, 3730, 7460, 8167,
+ 6753, 4461, 1909, 3818, 7636, 7687, 6561, 5869, 2165, 4330,
+ 1147, 2294, 4588, 1655, 3310, 6620, 5655, 2433, 4866, 939,
+ 1878, 3756, 7512, 7967, 7057, 4749, 181, 362, 724, 1448, 2896,
+ 5792, 2287, 4574, 1555, 3110, 6220, 5431, 4033, 8066, 6827,
+ 4345, 1117, 2234, 4468, 1863, 3726, 7452, 8087, 6785, 4269,
+ 1269, 2538, 5076, 519, 1038, 2076, 4152, 1503, 3006, 6012,
+ 2903, 5806, 2291, 4582, 1635, 3270, 6540, 5815, 2241, 4482,
+ 1707, 3414, 6828, 4343, 1089, 2178, 4356, 1959, 3918, 7836,
+ 6295, 5249, 3245, 6490, 5915, 2969, 5938, 3019, 6038, 2691,
+ 5382, 4003, 8006, 6947, 5097, 637, 1274, 2548, 5096, 639,
+ 1278, 2556, 5112, 607, 1214, 2428, 4856, 95, 190, 380, 760,
+ 1520, 3040, 6080, 2607, 5214, 3347, 6694, 4579, 1641, 3282,
+ 6564, 5863, 2145, 4290, 1067, 2134, 4268, 1271, 2542, 5084,
+ 535, 1070, 2140, 4280, 1247, 2494, 4988, 855, 1710, 3420,
+ 6840, 4319, 1041, 2082, 4164, 1319, 2638, 5276, 3223, 6446,
+ 6131, 2633, 5266, 3211, 6422, 6019, 2729, 5458, 3851, 7702,
+ 6531, 5801, 2301, 4602, 1627, 3254, 6508, 6007, 2881, 5762,
+ 2219, 4438, 1795, 3590, 7180, 7607, 7873, 6189, 5621, 3653,
+ 7306, 7355, 7385, 7197, 7573, 7813, 6309, 5349, 3173, 6346,
+ 5179, 3545, 7090, 4811, 57, 114, 228, 456, 912, 1824, 3648,
+ 7296, 7343, 7409, 7245, 7477, 8133, 6693, 4581, 1637, 3274,
+ 6548, 5767, 2209, 4418, 1835, 3670, 7340, 7415, 7233, 7469,
+ 8181, 6725, 4389, 2021, 4042, 8084, 6791, 4257, 1261, 2522,
+ 5044, 711, 1422, 2844, 5688, 2527, 5054, 723, 1446, 2892,
+ 5784, 2207, 4414, 2003, 4006, 8012, 6967, 5057, 557, 1114,
+ 2228, 4456, 1919, 3838, 7676, 7767, 6401, 6061, 2805, 5610,
+ 3707, 7414, 7235, 7465, 8189, 6741, 4357, 1957, 3914, 7828,
+ 6279, 5281, 3309, 6618, 5659, 2457, 4914, 971, 1942, 3884,
+ 7768, 6431, 6033, 2701, 5402, 3995, 7990, 7107, 4649, 509,
+ 1018, 2036, 4072, 8144, 6671, 4529, 1741, 3482, 6964, 5063,
+ 545, 1090, 2180, 4360, 1983, 3966, 7932, 6231, 5377, 4013,
+ 8026, 6939, 5017, 669, 1338, 2676, 5352, 3199, 6398, 5203,
+ 3337, 6674, 4491, 1721, 3442, 6884, 4199, 1377, 2754, 5508,
+ 3751, 7502, 7987, 7113, 4669, 469, 938, 1876, 3752, 7504,
+ 7951, 7089, 4813, 53, 106, 212, 424, 848, 1696, 3392, 6784,
+ 4271, 1265, 2530, 5060, 551, 1102, 2204, 4408, 2015, 4030,
+ 8060, 6999, 4865, 941, 1882, 3764, 7528, 8063, 6993, 4877,
+ 949, 1898, 3796, 7592, 7935, 6225, 5389, 4021, 8042, 7035,
+ 4953, 797, 1594, 3188, 6376, 5247, 3409, 6818, 4331, 1145,
+ 2290, 4580, 1639, 3278, 6556, 5783, 2177, 4354, 1963, 3926,
+ 7852, 6391, 5185, 3373, 6746, 4379, 1945, 3890, 7780, 6503,
+ 5985, 2925, 5850, 2075, 4150, 1475, 2950, 5900, 2999, 5998,
+ 2931, 5862, 2147, 4294, 1059, 2118, 4236, 1207, 2414, 4828,
+ 23, 46, 92, 184, 368, 736, 1472, 2944, 5888, 2991, 5982, 2835,
+ 5670, 2531, 5062, 547, 1094, 2188, 4376, 1951, 3902, 7804,
+ 6487, 5889, 2989, 5978, 2843, 5686, 2499, 4998, 675, 1350,
+ 2700, 5400, 3999, 7998, 7123, 4617, 445, 890, 1780, 3560,
+ 7120, 4623, 433, 866, 1732, 3464, 6928, 5007, 689, 1378, 2756,
+ 5512, 3775, 7550, 8019, 6921, 5053, 725, 1450, 2900, 5800,
+ 2303, 4606, 1619, 3238, 6476, 5943, 3009, 6018, 2731, 5462,
+ 3843, 7686, 6563, 5865, 2173, 4346, 1115, 2230, 4460, 1911,
+ 3822, 7644, 7703, 6529, 5805, 2293, 4586, 1659, 3318, 6636,
+ 5751, 2369, 4738, 171, 342, 684, 1368, 2736, 5472, 3951, 7902,
+ 6163, 5513, 3773, 7546, 8027, 6937, 5021, 661, 1322, 2644,
+ 5288, 3327, 6654, 5715, 2313, 4626, 395, 790, 1580, 3160,
+ 6320, 5327, 3121, 6242, 5483, 3961, 7922, 6219, 5433, 4061,
+ 8122, 6875, 4121, 1437, 2874, 5748, 2375, 4750, 179, 358, 716,
+ 1432, 2864, 5728, 2415, 4830, 19, 38, 76, 152, 304, 608, 1216,
+ 2432, 4864, 943, 1886, 3772, 7544, 8031, 6929, 5005, 693,
+ 1386, 2772, 5544, 3839, 7678, 7763, 6409, 6077, 2773, 5546,
+ 3835, 7670, 7747, 6441, 6141, 2645, 5290, 3323, 6646, 5699,
+ 2345, 4690, 267, 534, 1068, 2136, 4272, 1231, 2462, 4924, 983,
+ 1966, 3932, 7864, 6367, 5137, 3469, 6938, 5019, 665, 1330,
+ 2660, 5320, 3135, 6270, 5459, 3849, 7698, 6539, 5817, 2269,
+ 4538, 1755, 3510, 7020, 4983, 833, 1666, 3332, 6664, 4543,
+ 1745, 3490, 6980, 4903, 993, 1986, 3972, 7944, 7103, 4817, 13,
+ 26, 52, 104, 208, 416, 832, 1664, 3328, 6656, 4527, 1777,
+ 3554, 7108, 4647, 481, 962, 1924, 3848, 7696, 6543, 5809,
+ 2253, 4506, 1691, 3382, 6764, 4471, 1857, 3714, 7428, 8103,
+ 6881, 4205, 1397, 2794, 5588, 3591, 7182, 7603, 7881, 6205,
+ 5589, 3589, 7178, 7611, 7897, 6173, 5525, 3717, 7434, 8123,
+ 6873, 4125, 1429, 2858, 5716, 2311, 4622, 435, 870, 1740,
+ 3480, 6960, 5071, 561, 1122, 2244, 4488, 1727, 3454, 6908,
+ 4183, 1281, 2562, 5124, 3495, 6990, 4915, 969, 1938, 3876,
+ 7752, 6463, 6097, 2573, 5146, 3483, 6966, 5059, 553, 1106,
+ 2212, 4424, 1855, 3710, 7420, 7255, 7425, 8109, 6901, 4165,
+ 1317, 2634, 5268, 3207, 6414, 6067, 2761, 5522, 3723, 7446,
+ 8067, 6825, 4349, 1109, 2218, 4436, 1799, 3598, 7196, 7575,
+ 7809, 6317, 5365, 3141, 6282, 5307, 3289, 6578, 5835, 2105,
+ 4210, 1355, 2710, 5420, 4087, 8174, 6771, 4425, 1853, 3706,
+ 7412, 7239, 7457, 8173, 6773, 4421, 1829, 3658, 7316, 7303,
+ 7329, 7405, 7285, 7493, 7973, 7141, 4709, 357, 714, 1428,
+ 2856, 5712, 2319, 4638, 403, 806, 1612, 3224, 6448, 6095,
+ 2609, 5218, 3435, 6870, 4099, 1449, 2898, 5796, 2279, 4558,
+ 1587, 3174, 6348, 5175, 3521, 7042, 4779, 249, 498, 996, 1992,
+ 3984, 7968, 7151, 4721, 333, 666, 1332, 2664, 5328, 3087,
+ 6174, 5523, 3721, 7442, 8075, 6841, 4317, 1045, 2090, 4180,
+ 1287, 2574, 5148, 3479, 6958, 5107, 585, 1170, 2340, 4680,
+ 319, 638, 1276, 2552, 5104, 591, 1182, 2364, 4728, 351, 702,
+ 1404, 2808, 5616, 3663, 7326, 7315, 7305, 7357, 7381, 7173,
+ 7589, 7909, 6245, 5477, 3941, 7882, 6203, 5593, 3613, 7226,
+ 7643, 7705, 6557, 5781, 2181, 4362, 1979, 3958, 7916, 6263,
+ 5441, 3885, 7770, 6427, 6041, 2717, 5434, 4059, 8118, 6851,
+ 4137, 1533, 3066, 6132, 2631, 5262, 3251, 6502, 5987, 2921,
+ 5842, 2059, 4118, 1411, 2822, 5644, 2487, 4974, 883, 1766,
+ 3532, 7064, 4767, 145, 290, 580, 1160, 2320, 4640, 495, 990,
+ 1980, 3960, 7920, 6223, 5425, 4045, 8090, 6811, 4249, 1181,
+ 2362, 4724, 327, 654, 1308, 2616, 5232, 3407, 6814, 4243,
+ 1161, 2322, 4644, 487, 974, 1948, 3896, 7792, 6479, 5937,
+ 3021, 6042, 2715, 5430, 4035, 8070, 6819, 4329, 1149, 2298,
+ 4596, 1607, 3214, 6428, 6039, 2689, 5378, 4011, 8022, 6915,
+ 5033, 765, 1530, 3060, 6120, 2687, 5374, 3155, 6310, 5347,
+ 3177, 6354, 5131, 3513, 7026, 4939, 825, 1650, 3300, 6600,
+ 5695, 2513, 5026, 747, 1494, 2988, 5976, 2847, 5694, 2515,
+ 5030, 739, 1478, 2956, 5912, 2975, 5950, 3027, 6054, 2787,
+ 5574, 3619, 7238, 7459, 8169, 6781, 4437, 1797, 3594, 7188,
+ 7559, 7841, 6381, 5237, 3397, 6794, 4283, 1241, 2482, 4964,
+ 871, 1742, 3484, 6968, 5087, 529, 1058, 2116, 4232, 1215,
+ 2430, 4860, 87, 174, 348, 696, 1392, 2784, 5568, 3631, 7262,
+ 7443, 8073, 6845, 4309, 1029, 2058, 4116, 1415, 2830, 5660,
+ 2455, 4910, 1011, 2022, 4044, 8088, 6815, 4241, 1165, 2330,
+ 4660, 455, 910, 1820, 3640, 7280, 7503, 7985, 7117, 4661, 453,
+ 906, 1812, 3624, 7248, 7439, 8113, 6861, 4149, 1477, 2954,
+ 5908, 2951, 5902, 2995, 5990, 2915, 5830, 2083, 4166, 1315,
+ 2630, 5260, 3255, 6510, 6003, 2889, 5778, 2187, 4374, 1923,
+ 3846, 7692, 6583, 5825, 2093, 4186, 1307, 2614, 5228, 3447,
+ 6894, 4211, 1353, 2706, 5412, 4071, 8142, 6707, 4553, 1597,
+ 3194, 6388, 5191, 3361, 6722, 4395, 2041, 4082, 8164, 6759,
+ 4449, 1901, 3802, 7604, 7879, 6177, 5613, 3701, 7402, 7291,
+ 7513, 7965, 7061, 4741, 165, 330, 660, 1320, 2640, 5280, 3311,
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+ 2690, 5380, 4007, 8014, 6963, 5065, 573, 1146, 2292, 4584,
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+ 6048, 2799, 5598, 3603, 7206, 7651, 7785, 6525, 5973, 2821,
+ 5642, 2491, 4982, 835, 1670, 3340, 6680, 4511, 1681, 3362,
+ 6724, 4391, 2017, 4034, 8068, 6823, 4321, 1133, 2266, 4532,
+ 1735, 3470, 6940, 5015, 641, 1282, 2564, 5128, 3519, 7038,
+ 4947, 777, 1554, 3108, 6216, 5439, 4049, 8098, 6891, 4217,
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+ 3865, 7730, 6603, 5689, 2525, 5050, 731, 1462, 2924, 5848,
+ 2079, 4158, 1491, 2982, 5964, 2871, 5742, 2419, 4838, 99, 198,
+ 396, 792, 1584, 3168, 6336, 5167, 3569, 7138, 4715, 377, 754,
+ 1508, 3016, 6032, 2703, 5406, 3987, 7974, 7139, 4713, 381,
+ 762, 1524, 3048, 6096, 2575, 5150, 3475, 6950, 5091, 617,
+ 1234, 2468, 4936, 831, 1662, 3324, 6648, 5727, 2321, 4642,
+ 491, 982, 1964, 3928, 7856, 6351, 5169, 3533, 7066, 4763, 153,
+ 306, 612, 1224, 2448, 4896, 1007, 2014, 4028, 8056, 7007,
+ 4881, 909, 1818, 3636, 7272, 7551, 8017, 6925, 5045, 709,
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+ 4402, 1995, 3990, 7980, 7159, 4673, 301, 602, 1204, 2408,
+ 4816, 15, 30, 60, 120, 240, 480, 960, 1920, 3840, 7680, 6575,
+ 5873, 2125, 4250, 1179, 2358, 4716, 375, 750, 1500, 3000,
+ 6000, 2895, 5790, 2195, 4390, 2019, 4038, 8076, 6839, 4289,
+ 1069, 2138, 4276, 1223, 2446, 4892, 919, 1838, 3676, 7352,
+ 7391, 7185, 7565, 7861, 6341, 5157, 3557, 7114, 4667, 473,
+ 946, 1892, 3784, 7568, 7823, 6321, 5325, 3125, 6250, 5499,
+ 3929, 7858, 6347, 5177, 3549, 7098, 4827, 25, 50, 100, 200,
+ 400, 800, 1600, 3200, 6400, 6063, 2801, 5602, 3691, 7382,
+ 7171, 7593, 7933, 6229, 5381, 4005, 8010, 6971, 5081, 541,
+ 1082, 2164, 4328, 1151, 2302, 4604, 1623, 3246, 6492, 5911,
+ 2945, 5890, 2987, 5974, 2819, 5638, 2467, 4934, 803, 1606,
+ 3212, 6424, 6047, 2705, 5410, 4075, 8150, 6659, 4521, 1789,
+ 3578, 7156, 4679, 289, 578, 1156, 2312, 4624, 399, 798, 1596,
+ 3192, 6384, 5199, 3377, 6754, 4459, 1913, 3826, 7652, 7783,
+ 6497, 5997, 2933, 5866, 2171, 4342, 1091, 2182, 4364, 1975,
+ 3950, 7900, 6167, 5505, 3757, 7514, 7963, 7065, 4765, 149,
+ 298, 596, 1192, 2384, 4768, 239, 478, 956, 1912, 3824, 7648,
+ 7791, 6513, 5965, 2869, 5738, 2427, 4854, 67, 134, 268, 536,
+ 1072, 2144, 4288, 1071, 2142, 4284, 1239, 2478, 4956, 791,
+ 1582, 3164, 6328, 5343, 3089, 6178, 5611, 3705, 7410, 7243,
+ 7481, 8157, 6677, 4485, 1701, 3402, 6804, 4231, 1185, 2370,
+ 4740, 167, 334, 668, 1336, 2672, 5344, 3183, 6366, 5139, 3465,
+ 6930, 5003, 697, 1394, 2788, 5576, 3647, 7294, 7507, 7945,
+ 7101, 4821, 5, 10, 20, 40, 80, 160, 320, 640, 1280, 2560,
+ 5120, 3503, 7006, 4883, 905, 1810, 3620, 7240, 7487, 8145,
+ 6669, 4533, 1733, 3466, 6932, 4999, 673, 1346, 2692, 5384,
+ 4031, 8062, 6995, 4873, 957, 1914, 3828, 7656, 7807, 6481,
+ 5901, 2997, 5994, 2939, 5878, 2115, 4230, 1187, 2374, 4748,
+ 183, 366, 732, 1464, 2928, 5856, 2159, 4318, 1043, 2086, 4172,
+ 1335, 2670, 5340, 3095, 6190, 5619, 3657, 7314, 7307, 7353,
+ 7389, 7189, 7557, 7845, 6373, 5221, 3429, 6858, 4155, 1497,
+ 2994, 5988, 2919, 5838, 2099, 4198, 1379, 2758, 5516, 3767,
+ 7534, 8051, 6985, 4925, 981, 1962, 3924, 7848, 6399, 5201,
+ 3341, 6682, 4507, 1689, 3378, 6756, 4455, 1889, 3778, 7556,
+ 7847, 6369, 5229, 3445, 6890, 4219, 1369, 2738, 5476, 3943,
+ 7886, 6195, 5577, 3645, 7290, 7515, 7961, 7069, 4757, 133,
+ 266, 532, 1064, 2128, 4256, 1263, 2526, 5052, 727, 1454, 2908,
+ 5816, 2271, 4542, 1747, 3494, 6988, 4919, 961, 1922, 3844,
+ 7688, 6591, 5841, 2061, 4122, 1435, 2870, 5740, 2423, 4846,
+ 115, 230, 460, 920, 1840, 3680, 7360, 7215, 7665, 7757, 6453,
+ 6085, 2597, 5194, 3387, 6774, 4419, 1833, 3666, 7332, 7399,
+ 7265, 7533, 8053, 6981, 4901, 997, 1994, 3988, 7976, 7167,
+ 4689, 269, 538, 1076, 2152, 4304, 1039, 2078, 4156, 1495,
+ 2990, 5980, 2839, 5678, 2547, 5094, 611, 1222, 2444, 4888,
+ 927, 1854, 3708, 7416, 7263, 7441, 8077, 6837, 4293, 1061,
+ 2122, 4244, 1159, 2318, 4636, 407, 814, 1628, 3256, 6512,
+ 5967, 2865, 5730, 2411, 4822, 3, 6, 12, 24, 48, 96, 192, 384,
+ 768, 1536, 3072, 6144, 5551, 3825, 7650, 7787, 6521, 5981,
+ 2837, 5674, 2555, 5110, 579, 1158, 2316, 4632, 415, 830, 1660,
+ 3320, 6640, 5711, 2353, 4706, 363, 726, 1452, 2904, 5808,
+ 2255, 4510, 1683, 3366, 6732, 4407, 1985, 3970, 7940, 7079,
+ 4833, 109, 218, 436, 872, 1744, 3488, 6976, 4911, 1009, 2018,
+ 4036, 8072, 6847, 4305, 1037, 2074, 4148, 1479, 2958, 5916,
+ 2967, 5934, 3059, 6118, 2659, 5318, 3107, 6214, 5411, 4073,
+ 8146, 6667, 4537, 1757, 3514, 7028, 4935, 801, 1602, 3204,
+ 6408, 6079, 2769, 5538, 3819, 7638, 7683, 6569, 5885, 2133,
+ 4266, 1275, 2550, 5100, 631, 1262, 2524, 5048, 735, 1470,
+ 2940, 5880, 2143, 4286, 1235, 2470, 4940, 823, 1646, 3292,
+ 6584, 5855, 2065, 4130, 1515, 3030, 6060, 2807, 5614, 3699,
+ 7398, 7267, 7529, 8061, 6997, 4869, 933, 1866, 3732, 7464,
+ 8191, 6737, 4365, 1973, 3946, 7892, 6151, 5537, 3821, 7642,
+ 7707, 6553, 5789, 2197, 4394, 2043, 4086, 8172, 6775, 4417,
+ 1837, 3674, 7348, 7367, 7201, 7661, 7797, 6469, 5925, 3045,
+ 6090, 2619, 5238, 3395, 6790, 4259, 1257, 2514, 5028, 743,
+ 1486, 2972, 5944, 3039, 6078, 2771, 5542, 3811, 7622, 7715,
+ 6633, 5757, 2389, 4778, 251, 502, 1004, 2008, 4016, 8032,
+ 7023, 4977, 845, 1690, 3380, 6760, 4479, 1873, 3746, 7492,
+ 7975, 7137, 4717, 373, 746, 1492, 2984, 5968, 2831, 5662,
+ 2451, 4902, 995, 1990, 3980, 7960, 7071, 4753, 141, 282, 564,
+ 1128, 2256, 4512, 1775, 3550, 7100, 4823, 0
+};
+
+static int err_loc_ply[100][100];
+
+static int
+fix_section(unsigned long offset, void *data, int *syndromes_in)
+{
+ int i, j, elp_sum;
+ int syndromes[9];
+ int Matrix_a[11];
+ int Matrix_b[11];
+ int Matrix_c[12];
+ int Element[7];
+ int alpha;
+ int temp_index;
+ int data_location, rev_location;
+ int result_byte, result_bit;
+ int err_location[20];
+ int err_count;
+ int d_flg;
+ int block_length, data_length;
+
+ /* correct 4 bits in 512 bytes */
+ data_length = 4096;
+ block_length = 8191;
+
+ /*
+ If there are no errors, just return.
+ */
+
+ j = 0;
+
+ for (i = 0; i < 8; ++i) {
+ if (0 != syndromes_in[i]) {
+ j = 1;
+ break;
+ }
+ }
+
+ if (0 == j)
+ return 0;
+
+ /*
+ Decode.
+ */
+
+ memcpy((void *)syndromes, (void *)syndromes_in, sizeof(int) * 9);
+ d_flg = 0;
+
+ /* initialise table entries */
+ for (i = 0; i < 8; i++)
+ syndromes[i] = i_to_a[syndromes[i]];
+
+ Matrix_c[0] = 0;
+ Matrix_c[1] = syndromes[0];
+ err_loc_ply[0][0] = 1;
+ err_loc_ply[1][0] = 1;
+ for (i = 1; i < 8; i++) {
+ err_loc_ply[0][i] = 0;
+ err_loc_ply[1][i] = 0;
+ }
+ Matrix_a[0] = 0;
+ Matrix_a[1] = 0;
+ Matrix_b[0] = -1;
+ Matrix_b[1] = 0;
+ alpha = -1;
+
+ do {
+ /* skip even loops */
+ alpha += 2;
+ if (Matrix_c[alpha] != -1) {
+ temp_index = alpha - 2;
+ if (temp_index < 0)
+ temp_index = 0;
+ while ((Matrix_c[temp_index] == -1) && (temp_index > 0))
+ temp_index = temp_index - 2;
+ if (temp_index < 0)
+ temp_index = 0;
+
+ if (temp_index > 0) {
+ j = temp_index;
+ do {
+ j = j - 2;
+ if (j < 0)
+ j = 0;
+ if ((Matrix_c[j] != -1) &&
+ (Matrix_b[temp_index] < Matrix_b[j]))
+ temp_index = j;
+ } while (j > 0);
+ }
+
+ if (Matrix_a[alpha] > Matrix_a[temp_index] +
+ alpha - temp_index)
+ Matrix_a[alpha + 2] = Matrix_a[alpha];
+ else
+ Matrix_a[alpha + 2] = Matrix_a[temp_index] +
+ alpha - temp_index;
+
+ for (i = 0; i < 8; ++i)
+ err_loc_ply[alpha + 2][i] = 0;
+
+ for (i = 0; i <= Matrix_a[temp_index]; i++) {
+ if (err_loc_ply[temp_index][i] != 0)
+ err_loc_ply[alpha + 2][i +
+ alpha - temp_index] =
+ a_to_i[(Matrix_c[alpha] +
+ block_length -
+ Matrix_c[temp_index] +
+ i_to_a[err_loc_ply[temp_index]
+ [i]]) % block_length];
+ }
+
+ for (i = 0; i <= Matrix_a[alpha]; i++)
+ err_loc_ply[alpha + 2][i] ^=
+ err_loc_ply[alpha][i];
+ } else {
+ Matrix_a[alpha + 2] = Matrix_a[alpha];
+
+ for (i = 0; i <= Matrix_a[alpha]; i++)
+ err_loc_ply[alpha + 2][i] =
+ err_loc_ply[alpha][i];
+ }
+
+ Matrix_b[alpha + 2] = alpha+1 - Matrix_a[alpha + 2];
+
+ /* Form (alpha+2)th discrepancy. */
+ if (alpha < 8) {
+ if (syndromes[alpha + 1] != -1)
+ Matrix_c[alpha + 2] =
+ a_to_i[syndromes[alpha + 1]];
+ else
+ Matrix_c[alpha + 2] = 0;
+
+ for (i = 1; i <= Matrix_a[alpha + 2]; i++) {
+ if ((syndromes[alpha + 1 - i] != -1) &&
+ (err_loc_ply[alpha + 2][i] != 0))
+ Matrix_c[alpha + 2] ^=
+ a_to_i[(syndromes[alpha + 1 - i]
+ + i_to_a[err_loc_ply[alpha + 2]
+ [i]]) % block_length];
+ }
+ Matrix_c[alpha + 2] = i_to_a[Matrix_c[alpha + 2]];
+ }
+ } while ((alpha < 7) && (Matrix_a[alpha + 2] <= 4));
+
+ alpha = alpha+2;
+ Matrix_a[7] = Matrix_a[alpha];
+ if (Matrix_a[7] <= 4) {
+ for (i = 1; i <= Matrix_a[7]; i++)
+ Element[i] = i_to_a[err_loc_ply[alpha][i]];
+
+ err_count = 0;
+ for (i = 1; i <= block_length; i++) {
+ elp_sum = 1;
+ for (j = 1; j <= Matrix_a[7]; j++)
+ if (Element[j] != -1) {
+ Element[j] = (Element[j] + j) %
+ block_length;
+ elp_sum ^= a_to_i[Element[j]];
+ }
+
+ if (!elp_sum) {
+ err_location[err_count] = block_length - i;
+ err_count++;
+ }
+ }
+
+ if (err_count == Matrix_a[7])
+ d_flg = 1;
+ }
+
+ if (d_flg == 0)
+ return -1;
+ else {
+ for (i = 0; i < err_count; i++) {
+ if (err_location[i] >= 52)
+ data_location = err_location[i] - 52;
+ else
+ data_location = err_location[i] + data_length;
+
+ if (data_location <= 4095) {
+ rev_location = 4095 - data_location;
+ result_bit = rev_location % 8;
+ result_byte = (rev_location - result_bit) / 8;
+
+ pr_notice("Corrected ECC Error: offset 0x%lx byte 0x%x bit %d\n",
+ offset, result_byte, result_bit);
+
+ result_byte =
+ (result_byte & 0xfffffffc) |
+ ((result_byte & 0x3) ^ 0x3);
+ *((unsigned char *)(data +
+ result_byte)) ^=
+ (1 << result_bit);
+ } else {
+ rev_location = 4147 - data_location;
+ result_bit = rev_location % 8;
+ result_byte = (rev_location - result_bit) / 8;
+ pr_err("BCH byte = %d, bit = %d\n",
+ result_byte, result_bit);
+ }
+ }
+
+ if (0 != err_count)
+ return 1;
+ else
+ return 0;
+ }
+}
+
+/*
+ ------------------------------------------------------------------------------
+ report_ecc_errors_ep501g1
+*/
+
+static int
+report_ecc_errors_ep501g1(struct mtd_info *mtd, struct nand_chip *chip,
+ uint8_t *buffer, int page)
+{
+ unsigned long ecc_status;
+ int i;
+
+ for (i = 0; i < (mtd->writesize / 1024); ++i) {
+ ecc_status = readl(chip->IO_ADDR_R +
+ EP501G1_NAND_1BIT_ECC0_STATUS + (i * 4));
+
+ switch (ecc_status & (3 << 12)) {
+ case 01:
+ pr_err("Correctable ECC Error: %d:0x%lx\n",
+ i, ecc_status);
+ break;
+ case 02:
+ pr_err("Uncorrectable ECC Error: %d:0x%lx\n",
+ i, ecc_status);
+ break;
+ }
+ }
+
+ return 0;
+}
+
+/*
+ ------------------------------------------------------------------------------
+ report_ecc_errors_ep501g3
+*/
+
+static int
+report_ecc_errors_ep501g3(struct mtd_info *mtd, struct nand_chip *chip,
+ uint8_t *buffer, int page)
+{
+ unsigned long bch_status;
+ int rc = 0;
+ unsigned long value;
+ int i;
+ int is_blank = 1;
+ uint8_t *data = buffer;
+ int section;
+ int syndrome;
+ unsigned long syndromes[8][8];
+
+ /* Verify 4-bit mode in the EP501G3 case. */
+ value = (READL(chip->IO_ADDR_R + EP501_NAND_CONFIG_REG) & 0x1800) >> 11;
+
+ if (1 != value) {
+ pr_err("Only 4-Bit ECC is supported.\n");
+ rc = -1;
+ goto report_ecc_errors_ep501g3_end;
+ }
+
+ /* If there are no errors, return. */
+ bch_status = READL(chip->IO_ADDR_R + EP501G1_NAND_BCH_STATUS);
+
+ if (0 == bch_status)
+ goto report_ecc_errors_ep501g3_end;
+
+ switch (mtd->writesize) {
+ case 512:
+ bch_status &= 0x1;
+ break;
+ case 2048:
+ bch_status &= 0xf;
+ break;
+ case 4096:
+ bch_status &= 0xff;
+ break;
+ default:
+ pr_err("Unexpected Page Size!\n");
+ rc = -1;
+ goto report_ecc_errors_ep501g3_end;
+ }
+
+ /* Ignore fully erased blocks. */
+ if (NULL != data) {
+ for (i = 0; i < mtd->writesize; ++i) {
+ if (0xff != *data++) {
+ is_blank = 0;
+ break;
+ }
+ }
+ }
+
+ if (0 != is_blank)
+ goto report_ecc_errors_ep501g3_end;
+
+ /* Read the syndrome registers and split them into syndromes. */
+ for (section = 0; section < 8; ++section) {
+ unsigned long address;
+ unsigned long value;
+
+ address = EP501G1_NAND_SYN_R12_S0 + (section * 0x10);
+
+ for (syndrome = 0; syndrome < ((mtd->writesize / 512) * 2);
+ syndrome += 2, address += 4) {
+ value = READL(chip->IO_ADDR_R + address);
+ syndromes[section][syndrome] =
+ (value & 0x1fff);
+ syndromes[section][syndrome + 1] =
+ ((value & 0x1fff0000) >> 16);
+ }
+ }
+
+#ifdef NOT_USED
+ /* Debug output (BCH status register and syndromes). */
+ pr_info("BCH Status Register: 0x%02lx\n", bch_status);
+
+ for (section = 0; section < 8; ++section) {
+ pr_info("Syndromes, Section %d: ", section);
+
+ for (syndrome = 0; syndrome < 8; ++syndrome)
+ pr_info("0x%04lx ",
+
+ pr_info("\n");
+ }
+#endif
+
+ for (i = 0; i < 4; ++i) {
+ if ((1 << i) == (bch_status & (1 << i))) {
+ rc = fix_section(((page * mtd->writesize) + (512 * i)),
+ (void *)(buffer + (512 * i)),
+ (int *)&syndromes[i]);
+
+ if (-1 == rc)
+ pr_err("Uncorrectable ECC Error: Page %d\n",
+ page);
+ }
+ }
+
+ report_ecc_errors_ep501g3_end:
+
+ return rc;
+}
+
+/*
+ ------------------------------------------------------------------------------
+ report_ecc_errors
+*/
+
+static int
+report_ecc_errors(struct mtd_info *mtd, struct nand_chip *chip,
+ uint8_t *buffer, int page)
+{
+ int rc = 0;
+
+ switch (lsi_nand_type) {
+ case LSI_NAND_EP501:
+ rc = report_ecc_errors_ep501(mtd, chip, buffer, page);
+ break;
+ case LSI_NAND_EP501G1:
+ rc = report_ecc_errors_ep501g1(mtd, chip, buffer, page);
+ break;
+ case LSI_NAND_EP501G3:
+ rc = report_ecc_errors_ep501g3(mtd, chip, buffer, page);
+ break;
+ default:
+ rc = -1;
+ break;
+ }
+
+ return rc;
+}
+
+
+/**
+ * nand_read_page_hwecc - hardware ecc based page read function
+ * @mtd: mtd info structure
+ * @chip: nand chip info structure
+ * @buf: buffer to store read data
+ *
+ * Not for syndrome calculating ecc controllers which need a special oob layout
+ */
+
+static int
+lsi_nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
+ uint8_t *buf, int oob_required, int page)
+{
+ int rc;
+ /*int page = 0;*/
+
+ /* Read the current page number and save it. */
+ /*page = READL(chip->IO_ADDR_R + NAND_INDEX_REG) >> 12;*/
+
+ /* read the page */
+ chip->read_buf(mtd, buf, mtd->writesize);
+
+ /* read oob data */
+ chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
+
+ /* start ECC calculations */
+ chip->ecc.calculate(mtd, NULL, NULL);
+
+ /* Read the ECC Status and see if there were any errors */
+ rc = report_ecc_errors(mtd, chip, buf, page);
+
+ /* cmd to controller to turn off CE */
+ chip->cmd_ctrl(mtd, nand_cmd_ce_off, 0);
+ return rc;
+}
+
+/**
+ * lsi_nand_write_page_hwecc - hardware ecc based page write function
+ * @mtd: mtd info structure
+ * @chip: nand chip info structure
+ * @buf: data buffer
+ */
+static int
+lsi_nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
+ const uint8_t *buf, int oob_required)
+{
+ /* write the page data */
+ chip->write_buf(mtd, buf, mtd->writesize);
+
+ /*
+ * Write the oob data. Last 12 bytes are used by HW ECC.
+ * Do not touch them.
+ */
+ chip->write_buf(mtd, chip->oob_poi, mtd->oobsize - chip->ecc.bytes);
+ return 0;
+}
+
+/**
+ * lsi_nand_write_page - [REPLACEABLE] write one page
+ * @mtd: MTD device structure
+ * @chip: NAND chip descriptor
+ * @buf: the data to write
+ * @page: page number to write
+ * @cached: cached programming
+ * @raw: use _raw version of write_page
+ */
+
+static int
+lsi_nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
+ uint32_t offset, int data_len, const uint8_t *buf,
+ int oob_required, int page, int cached, int raw)
+{
+ int status;
+
+ chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
+
+ if (unlikely(raw))
+ chip->ecc.write_page_raw(mtd, chip, buf, 0);
+ else
+ chip->ecc.write_page(mtd, chip, buf, 0);
+
+ /* calculate ECC */
+ status = chip->ecc.calculate(mtd, NULL, NULL);
+
+ /* cmd to controller to turn off CE */
+ chip->cmd_ctrl(mtd, nand_cmd_ce_off, 0);
+
+ /*
+ * See if operation failed and additional status checks are
+ * available
+ */
+ if (status & NAND_STATUS_FAIL) {
+ pr_err("ERROR: Page write failed for page 0x%x\n",
+ page);
+
+ if (chip->errstat)
+ status = chip->errstat(mtd, chip, FL_WRITING, status,
+ page);
+
+ return -EIO;
+ }
+
+ return 0;
+}
+
+
+/**
+ * lsi_nand_read_oob_std - [REPLACABLE] the most common OOB data read function
+ * @mtd: mtd info structure
+ * @chip: nand chip info structure
+ * @page: page number to read
+ * @sndcmd: flag whether to issue read command or not
+ */
+
+static int
+lsi_nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
+ int page)
+{
+ int rc;
+
+ /* send command to read oob */
+ chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
+
+ /* read oob data */
+ chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
+
+ /* start ECC calculations */
+ chip->ecc.calculate(mtd, NULL, NULL);
+
+ /* Read the ECC Status and see if there were any errors */
+ rc = report_ecc_errors(mtd, chip, NULL, page);
+
+ /* cmd to controller to turn off CE */
+ chip->cmd_ctrl(mtd, nand_cmd_ce_off, 0);
+
+ return 0;
+}
+
+/**
+ * lsi_nand_write_oob_std - [REPLACABLE] the most common OOB data write
+ * function
+ * @mtd: mtd info structure
+ * @chip: nand chip info structure
+ * @page: page number to write
+ */
+
+static int
+lsi_nand_write_oob(struct mtd_info *mtd, struct nand_chip *chip, int page)
+{
+ /* start OOB write */
+ chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
+
+ /*
+ * Write the oob data. Last 12 bytes are used by HW ECC.
+ * Do not touch them.
+ */
+ chip->write_buf(mtd, chip->oob_poi, mtd->oobsize - chip->ecc.bytes);
+
+ /* calculate ECC */
+ chip->ecc.calculate(mtd, NULL, NULL);
+
+ /* cmd to controller to turn off CE */
+ chip->cmd_ctrl(mtd, nand_cmd_ce_off, 0);
+
+ return (chip->dev_ready(mtd) & NAND_STATUS_FAIL) ? -EIO : 0;
+}
+
+/*
+ ======================================================================
+ ======================================================================
+ Public
+ ======================================================================
+ ======================================================================
+*/
+
+/*
+ ------------------------------------------------------------------------------
+ lsi_nand_set_config
+*/
+
+int
+lsi_nand_set_config(struct mtd_info *mtd, struct nand_chip *chip)
+{
+ unsigned long config = 0;
+ unsigned long mbits;
+
+ mbits = ((chip->chipsize >> 20) * 8);
+
+ if (LSI_NAND_EP501 == lsi_nand_type) {
+ /* The EP501 only supports 512 and 2k page sizes. */
+ if (512 != mtd->writesize &&
+ 2048 != mtd->writesize)
+ return -1;
+
+ while (64 < mbits) {
+ ++config; /* 0b000=64Mbit, 0b001=128Mbit, etc. */
+ mbits >>= 1;
+ }
+
+ if (512 < mtd->writesize)
+ config |= 0x100; /* large block */
+
+ config |= 0x200; /* not write protected */
+ chip->ecc.layout = &lsi_2k_1bit_ecclayout;
+ chip->ecc.size = mtd->writesize;
+ chip->ecc.bytes = chip->ecc.layout->eccbytes;
+ chip->ecc.strength = 1;
+ } else if (LSI_NAND_EP501G1 == lsi_nand_type) {
+ /* The EP501G1 only supports 512, 2k, and 4k page sizes, */
+ if (512 != mtd->writesize &&
+ 2048 != mtd->writesize &&
+ 4096 != mtd->writesize)
+ return -1;
+
+ /* and device sizes as follows. */
+ if (512 == mtd->writesize) {
+ switch (mbits) {
+ case 64:
+ break;
+ case 128:
+ config |= 1;
+ break;
+ case 256:
+ config |= 2;
+ break;
+ case 512:
+ config |= 3;
+ break;
+ case 1024:
+ config |= 4;
+ break;
+ case 2048:
+ config |= 5;
+ break;
+ case 4096:
+ config |= 6;
+ break;
+ case 8192:
+ config |= 7;
+ break;
+ default:
+ return -1;
+ }
+ } else {
+ switch (mbits) {
+ case 512:
+ config |= 3;
+ break;
+ case 1024:
+ config |= 4;
+ break;
+ case 2048:
+ config |= 5;
+ break;
+ case 4096:
+ config |= 6;
+ break;
+ case 8192:
+ config |= 7;
+ break;
+ case 16384:
+ break;
+ case 32768:
+ config |= 1;
+ break;
+ case 65536:
+ config |= 2;
+ break;
+ default:
+ return -1;
+ }
+ }
+
+ switch (mtd->writesize) {
+ case 512:
+ break;
+ case 2048:
+ config |= 0x1 << 8;
+ chip->ecc.layout = &lsi_2k_4bit_ecclayout;
+ break;
+ case 4096:
+ config |= 0x2 << 8;
+ chip->ecc.layout = &lsi_4k_4bit_ecclayout;
+ break;
+ default:
+ return -1;
+ }
+
+ config |= 1 << 10; /* not write protected */
+
+ config |= 1 << 11; /* 4 bit ECC */
+
+ if (512 < mtd->writesize)
+ config |= 1 << 12; /* 3 cycle row address */
+
+ chip->ecc.size = mtd->writesize;
+
+ if (mtd->oobsize == 224)
+ chip->ecc.bytes = 224 - chip->ecc.layout->eccbytes;
+ else
+ chip->ecc.bytes = chip->ecc.layout->eccbytes;
+
+ chip->ecc.strength = 4;
+
+ } else if (LSI_NAND_EP501G3 == lsi_nand_type) {
+ /* The EP501G3 only supports 2k, 4k, and 8k page sizes, */
+ if (2048 != mtd->writesize &&
+ 4096 != mtd->writesize &&
+ 8192 != mtd->writesize)
+ return -1;
+
+ /* and device sizes as follows. */
+ switch (mbits) {
+ case 512:
+ config |= 3;
+ break;
+ case 1024:
+ config |= 4;
+ break;
+ case 2048:
+ config |= 5;
+ break;
+ case 4096:
+ config |= 6;
+ break;
+ case 8192:
+ config |= 7;
+ break;
+ case 16384:
+ break;
+ case 32768:
+ config |= 1;
+ break;
+ case 65536:
+ config |= 2;
+ break;
+ default:
+ pr_err("Invalid Device Size: 0x%lx\n", mbits);
+ return -1;
+ }
+
+ switch (mtd->writesize) {
+ case 2048:
+ config |= 0x1 << 8;
+ chip->ecc.layout = &lsi_2k_4bit_ecclayout;
+ break;
+ case 4096:
+ config |= 0x2 << 8;
+ chip->ecc.layout = &lsi_4k_4bit_ecclayout;
+ break;
+#ifdef NOT_USED
+ case 8192:
+ config |= 0x3 << 8;
+ chip->ecc.layout = &lsi_8k_4bit_ecclayout;
+ break;
+#endif
+ default:
+ return -1;
+ }
+
+ config |= 1 << 10; /* not write protected */
+ config |= 1 << 13; /* 3 cycle row address */
+
+ /*
+ 2K/4bit - 32 bytes (8192)
+ 2K/8bit - 64 bytes (16384)
+ 2K/12bit - 80 bytes (24576)
+ ...
+ 8K/12bit - 320 bytes (98304)
+ */
+
+ if (mtd->oobsize < chip->ecc.layout->eccbytes) {
+ pr_err("ECC requires %d bytes, only %d are available\n",
+ chip->ecc.layout->eccbytes, mtd->oobsize);
+ return -1;
+ }
+
+ config |= 1 << 11; /* 4 bit ECC */
+ mtd->oobavail = mtd->oobsize - chip->ecc.layout->eccbytes;
+ mtd->oobavail -= (mtd->oobavail % 4);
+ config |= (chip->ecc.layout->eccbytes / 4) << 16;
+ chip->ecc.size = mtd->writesize;
+ chip->ecc.bytes = chip->ecc.layout->eccbytes;
+ chip->ecc.strength = 4;
+ } else {
+ return -1;
+ }
+
+ WRITEL(config, chip->IO_ADDR_W + EP501_NAND_CONFIG_REG);
+
+ return 0;
+}
+
+static uint8_t
+lsi_nand_read_byte(struct mtd_info *mtd)
+{
+ struct lsi_nand_private *priv = &lsi_nand_private;
+ struct nand_chip *chip = mtd->priv;
+
+ if (priv->cur >= 0) {
+ WARN_ON(priv->cur >= MAX_READ_BUF);
+ return priv->buf[priv->cur++];
+ } else
+ return readb(chip->IO_ADDR_R);
+}
+
+static int lsi_nand_errstat
+ (struct mtd_info *mtd, struct nand_chip *chip,
+ int state, int status, int page) {
+ /* if erase failed for a block, mark it as bad block */
+ if ((FL_ERASING == chip->state) && (status & NAND_STATUS_FAIL))
+ mtd_block_markbad(mtd, page << chip->page_shift);
+
+ return status;
+}
+
+static int
+lsi_nand_init_size(struct mtd_info *mtd, struct nand_chip *chip, u8 *id_data)
+{
+ int busw, extid;
+
+ /* The 3rd id byte holds MLC / multichip data */
+ chip->cellinfo = readb(chip->IO_ADDR_R + NAND_ID4_REG);
+ /* The 4th id byte is the important one */
+ extid = readb(chip->IO_ADDR_R + NAND_ID6_REG);
+
+ /* Add workaournd for Micron MT29Fxxxxxx NAND flash */
+ if (id_data[0] == NAND_MFR_MICRON && id_data[1] == 0x48) {
+ /* Calc pagesize */
+ mtd->writesize = 1024 << (extid & 0x03);
+ extid >>= 2;
+ /*Calc oobsize */
+ mtd->oobsize = ((extid & 0x03) == 0x03) ? 218 : 224;
+ extid >>= 3;
+ /* Calc blocksize. Blocksize is multiples of 256KiB */
+ mtd->erasesize = (256 * 1024) << (extid & 0x03);
+ busw = 0;
+ } else {
+ /* Calc pagesize */
+ mtd->writesize = 1024 << (extid & 0x03);
+ extid >>= 2;
+ /* Calc oobsize */
+ mtd->oobsize = (8 << (extid & 0x01)) * (mtd->writesize >> 9);
+ extid >>= 2;
+ /* Calc blocksize. Blocksize is multiples of 64KiB */
+ mtd->erasesize = (64 * 1024) << (extid & 0x03);
+ extid >>= 2;
+ /* Get buswidth information */
+ busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
+ }
+
+ lsi_nand_set_config(mtd, chip);
+
+ return busw;
+}
+
+/*
+ ----------------------------------------------------------------------
+ lsi_nand_init
+*/
+
+#define NAND_BASE 0x002000440000ULL
+#define NAND_SIZE 0x20000
+#define GPREG_BASE 0x00200040c000ULL
+#define GPREG_SIZE 0x1000
+
+static int __init
+lsi_nand_init(void)
+{
+ void *nand_base;
+ struct device_node *np = NULL;
+ struct mtd_part_parser_data ppdata;
+ static const char *part_probe_types[]
+ = { "cmdlinepart", "ofpart", NULL };
+ const u32 *reg;
+ int reglen;
+ u64 nand_address;
+ unsigned long nand_length;
+ u64 gpreg_address;
+ unsigned long gpreg_length;
+ const u32 *enabled;
+ unsigned long cr;
+ unsigned long cr_save;
+
+ memset(&ppdata, 0, sizeof(ppdata));
+
+ np = of_find_node_by_type(np, "nand");
+
+ while (np && !of_device_is_compatible(np, "acp-nand"))
+ np = of_find_node_by_type(np, "nand");
+
+ if (NULL == np) {
+ pr_err("No NAND Nodes in Device Tree\n");
+
+ return -1;
+ }
+
+ enabled = of_get_property(np, "enabled", NULL);
+
+ if (!enabled || (enabled && (0 == *enabled))) {
+ pr_err("ACP NAND Controller Isn't Enabled.\n");
+ return -ENODEV;
+ }
+
+ reg = of_get_property(np, "reg", ®len);
+
+ if (reg && (16 == reglen)) {
+ nand_address = of_translate_address(np, reg);
+ nand_length = reg[1];
+ reg += 2;
+ gpreg_address = of_translate_address(np, reg);
+ gpreg_length = reg[1];
+ pr_info("nand_address=0x%08llx nand_length=0x%lx\n"
+ "gpreg_address=0x%08llx gpreg_length=0x%lx\n",
+ nand_address, nand_length,
+ gpreg_address, gpreg_length);
+ nand_base = ioremap(nand_address, nand_length);
+ gpreg_base = ioremap(gpreg_address, gpreg_length);
+ } else {
+ return -1;
+ }
+
+ ppdata.of_node = np;
+
+ /*
+ Determine the Axxia system type.
+
+ The ECC status register and mask are different on 344x, 342x, 35xx...
+ */
+
+ if (of_machine_is_compatible("lsi,acp3500")) {
+ pecc_busy_register = (gpreg_base + 0x8c);
+ pecc_busy_mask = (1 << 20);
+ } else {
+ if (of_machine_is_compatible("lsi,acp3420")) {
+ pecc_busy_register = (gpreg_base + 0xc);
+ pecc_busy_mask = (1 << 28);
+ } else {
+ if (of_machine_is_compatible("lsi,acp3440")) {
+ pecc_busy_register = (gpreg_base + 0xc);
+ pecc_busy_mask = (1 << 28);
+ } else {
+ pr_err("Unsupported NAND Target\n");
+
+ return -1;
+ }
+ }
+ }
+
+ /*
+ Determine the version of the controller.
+
+ As there is not version register, see if bits 5:3 of the
+ configuration register are writable. There are in the EP501
+ case and aren't in the EP501G1 case.
+ */
+
+ cr = cr_save = READL((void *)(nand_base + NAND_CONFIG_REG));
+ cr = 0x2038;
+ WRITEL(cr, (void *)(nand_base + EP501_NAND_CONFIG_REG));
+ cr = READL((void *)nand_base + EP501_NAND_CONFIG_REG);
+ WRITEL(cr_save, (void *)(nand_base + EP501_NAND_CONFIG_REG));
+
+ if (0 == (cr & 0x2038))
+ lsi_nand_type = LSI_NAND_EP501G1;
+ else if (0x38 == (cr & 0x2038))
+ lsi_nand_type = LSI_NAND_EP501;
+ else if (0x2000 == (cr & 0x2038))
+ lsi_nand_type = LSI_NAND_EP501G3;
+ else
+ lsi_nand_type = LSI_NAND_NONE;
+
+ switch (lsi_nand_type) {
+ case LSI_NAND_EP501:
+ pr_info("EP501 NAND Controller.\n");
+ nand_cmd_ce_off = NAND_CMD_CE_OFF_501;
+ break;
+ case LSI_NAND_EP501G1:
+ pr_info("EP501G1 NAND Controller.\n");
+ nand_cmd_ce_off = NAND_CMD_CE_OFF_501G1;
+ break;
+ case LSI_NAND_EP501G3:
+ pr_info("EP501G3 NAND Controller.\n");
+ nand_cmd_ce_off = NAND_CMD_CE_OFF_501G3;
+ break;
+ default:
+ pr_info("Unknown NAND Controller!\n");
+ return -1;
+ }
+
+ /* Initialize structures */
+ memset(&lsi_nand_mtd, 0, sizeof(struct mtd_info));
+ memset(&lsi_nand_chip, 0, sizeof(struct nand_chip));
+
+ /* Link the private data with the MTD structure */
+ lsi_nand_mtd.priv = &lsi_nand_chip;
+ lsi_nand_mtd.owner = THIS_MODULE;
+ lsi_nand_mtd.name = "acp-nand";
+
+ /* init chip callbacks */
+ lsi_nand_chip.IO_ADDR_R = (void *) nand_base;
+ lsi_nand_chip.IO_ADDR_W = (void *) nand_base;
+ lsi_nand_chip.write_buf = lsi_nand_write_buf;
+ lsi_nand_chip.read_buf = lsi_nand_read_buf;
+ lsi_nand_chip.write_page = lsi_nand_write_page;
+ lsi_nand_chip.cmd_ctrl = lsi_nand_hwcontrol;
+ lsi_nand_chip.dev_ready = lsi_nand_device_ready;
+ lsi_nand_chip.cmdfunc = lsi_nand_command;
+ lsi_nand_chip.waitfunc = lsi_nand_wait;
+ lsi_nand_chip.chip_delay = 10;
+ lsi_nand_chip.bbt_options = NAND_BBT_USE_FLASH;
+ lsi_nand_chip.read_byte = lsi_nand_read_byte;
+ lsi_nand_chip.errstat = lsi_nand_errstat;
+ lsi_nand_chip.init_size = lsi_nand_init_size;
+
+ /* initialize ECC */
+ lsi_nand_chip.ecc.mode = NAND_ECC_HW;
+ lsi_nand_chip.ecc.steps = 1;
+ lsi_nand_chip.ecc.total = 12;
+ lsi_nand_chip.ecc.hwctl = lsi_nand_ecc_hwctl;
+ lsi_nand_chip.ecc.calculate = lsi_nand_ecc_calculate;
+ lsi_nand_chip.ecc.correct = lsi_nand_ecc_correct;
+ lsi_nand_chip.ecc.read_page = lsi_nand_read_page_hwecc;
+ lsi_nand_chip.ecc.write_page = lsi_nand_write_page_hwecc;
+ lsi_nand_chip.ecc.read_page_raw = lsi_nand_read_page_hwecc;
+ lsi_nand_chip.ecc.write_page_raw = lsi_nand_write_page_hwecc;
+ lsi_nand_chip.ecc.read_oob = lsi_nand_read_oob;
+ lsi_nand_chip.ecc.write_oob = lsi_nand_write_oob;
+
+ pr_err("Enabling NAND ECC...\n");
+ /* clear any existing ECC status */
+ WRITEL(0x0, lsi_nand_chip.IO_ADDR_W + NAND_INTR_STATUS_REG);
+ /* enable ECC */
+ WRITEL(0x0, lsi_nand_chip.IO_ADDR_W + NAND_INTR_EN_REG);
+
+ /*
+ ======================================================================
+ Timing Control
+
+ This may need to be changed, based on the devices used. Each field is
+ described below.
+ */
+
+ /*
+ TCR0 - NAND Timing Control Register 0
+ */
+
+ {
+ nand_timing_control_register_0_t tcr0;
+
+ /* TH [31:24] - CLE, CE & ALE hold Time */
+ tcr0.bits.th = 0x08;
+
+ /* TRP [23:16] - Read Pulse Width */
+ tcr0.bits.trp = 0x0c;
+
+ /* TWP [15:8] - Write Pulse Width */
+ tcr0.bits.twp = 0x0c;
+
+ /* TS [7:0] - Setup Time for CLE, CE & ALE */
+ tcr0.bits.ts = 0x05;
+
+ WRITEL(tcr0.raw,
+ (lsi_nand_chip.IO_ADDR_W + NAND_TIMING1_REG));
+ }
+
+ /*
+ TCR1 - NAND Timing Control Register 1
+ */
+
+ {
+ nand_timing_control_register_1_t tcr1;
+
+ /* TWB [31:24] - WE Rising Edge to RY/BY Falling Edge */
+ tcr1.bits.twb = 0x1e;
+
+ /* TRR [23:16] - RY/BY Rising Edge To Read Falling Edge */
+ tcr1.bits.trr = 0x07;
+
+ /* TRH [15:8] - Read Pulse High Time */
+ tcr1.bits.trh = 0x03;
+
+ /* TWH [7:0] - Write Pulse High Time */
+ tcr1.bits.twh = 0x03;
+
+ WRITEL(tcr1.raw,
+ (lsi_nand_chip.IO_ADDR_W + NAND_TIMING2_REG));
+ }
+
+ /*
+ TCR2 - NAND Timing Control Register 2 (EP501G3 Only)
+ */
+
+ {
+ nand_timing_control_register_2_t tcr2;
+
+ tcr2.bits.tccs = 0x10;
+ tcr2.bits.twhr = 0x10;
+ tcr2.bits.trhw = 0x14;
+ WRITEL(tcr2.raw,
+ (lsi_nand_chip.IO_ADDR_W + EP501G3_NAND_TIMING2_REG));
+ }
+
+ pr_err("Searching for NAND flash...\n");
+ /* Scan to find existence of the device */
+ if (nand_scan(&lsi_nand_mtd, 1)) {
+ pr_err("nand_scan failure...\n");
+ return -ENXIO;
+ }
+
+ /* Register the partitions */
+
+ mtd_device_parse_register(&lsi_nand_mtd, part_probe_types, &ppdata,
+ NULL, 0);
+
+ /* Return happy */
+ return 0;
+}
+
+module_init(lsi_nand_init);
+
+/*
+ ----------------------------------------------------------------------
+ lsi_nand_exit
+*/
+
+static void __exit
+lsi_nand_exit(void)
+{
+ /* Release resources, unregister device */
+ nand_release(&lsi_nand_mtd);
+}
+
+module_exit(lsi_nand_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Jay Jayatheerthan <jay.jayatheerthan at lsi.com>");
+MODULE_DESCRIPTION("MTD map driver for LSI's ACP board");
diff --git a/drivers/mtd/nand/lsi_ubootenv.c b/drivers/mtd/nand/lsi_ubootenv.c
new file mode 100644
index 0000000..1f46140
--- /dev/null
+++ b/drivers/mtd/nand/lsi_ubootenv.c
@@ -0,0 +1,570 @@
+/*
+ * drivers/lsi/acp/ubootenv.c
+ *
+ * Copyright (C) 2009 LSI
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 021.1.1_pre.17 USA
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/vmalloc.h>
+#include <linux/mtd/mtd.h>
+#include <linux/crc32.h>
+#include <linux/io.h>
+
+/*
+ ======================================================================
+ Data types and Macros
+ ======================================================================
+*/
+#include <asm/lsi/debug.h>
+
+/*
+ ======================================================================
+ Global Variables
+ ======================================================================
+*/
+
+static struct kobject *ubootenv_kobj;
+
+
+static unsigned long uboot_env_size = (128 * 1024);
+static unsigned long uboot_env_cs_size = (128 * 1024);
+static int uboot_env_current = -1;
+
+#define ENVIRONMENT_DATA_SIZE(size) (size - (2 * sizeof(unsigned long)))
+
+typedef struct environment {
+
+ unsigned long crc32;
+ unsigned long flags;
+ unsigned char data[];
+
+} __packed environment_t;
+
+static environment_t *environment = (environment_t *) 0;
+
+static unsigned long crc32_lut[256] = {
+
+ /* 0 -- */ 0u, 1996959894u, 3993919788u, 2567524794u,
+ /* 4 -- */ 124634137u, 1886057615u, 3915621685u, 2657392035u,
+ /* 8 -- */ 249268274u, 2044508324u, 3772115230u, 2547177864u,
+ /* 12 -- */ 162941995u, 2125561021u, 3887607047u, 2428444049u,
+ /* 16 -- */ 498536548u, 1789927666u, 4089016648u, 2227061214u,
+ /* 20 -- */ 450548861u, 1843258603u, 4107580753u, 2211677639u,
+ /* 24 -- */ 325883990u, 1684777152u, 4251122042u, 2321926636u,
+ /* 28 -- */ 335633487u, 1661365465u, 4195302755u, 2366115317u,
+ /* 32 -- */ 997073096u, 1281953886u, 3579855332u, 2724688242u,
+ /* 36 -- */ 1006888145u, 1258607687u, 3524101629u, 2768942443u,
+ /* 40 -- */ 901097722u, 1119000684u, 3686517206u, 2898065728u,
+ /* 44 -- */ 853044451u, 1172266101u, 3705015759u, 2882616665u,
+ /* 48 -- */ 651767980u, 1373503546u, 3369554304u, 3218104598u,
+ /* 52 -- */ 565507253u, 1454621731u, 3485111705u, 3099436303u,
+ /* 56 -- */ 671266974u, 1594198024u, 3322730930u, 2970347812u,
+ /* 60 -- */ 795835527u, 1483230225u, 3244367275u, 3060149565u,
+ /* 64 -- */ 1994146192u, 31158534u, 2563907772u, 4023717930u,
+ /* 68 -- */ 1907459465u, 112637215u, 2680153253u, 3904427059u,
+ /* 72 -- */ 2013776290u, 251722036u, 2517215374u, 3775830040u,
+ /* 76 -- */ 2137656763u, 141376813u, 2439277719u, 3865271297u,
+ /* 80 -- */ 1802195444u, 476864866u, 2238001368u, 4066508878u,
+ /* 84 -- */ 1812370925u, 453092731u, 2181625025u, 4111451223u,
+ /* 88 -- */ 1706088902u, 314042704u, 2344532202u, 4240017532u,
+ /* 92 -- */ 1658658271u, 366619977u, 2362670323u, 4224994405u,
+ /* 96 -- */ 1303535960u, 984961486u, 2747007092u, 3569037538u,
+ /* 100 -- */ 1256170817u, 1037604311u, 2765210733u, 3554079995u,
+ /* 104 -- */ 1131014506u, 879679996u, 2909243462u, 3663771856u,
+ /* 108 -- */ 1141124467u, 855842277u, 2852801631u, 3708648649u,
+ /* 112 -- */ 1342533948u, 654459306u, 3188396048u, 3373015174u,
+ /* 116 -- */ 1466479909u, 544179635u, 3110523913u, 3462522015u,
+ /* 120 -- */ 1591671054u, 702138776u, 2966460450u, 3352799412u,
+ /* 124 -- */ 1504918807u, 783551873u, 3082640443u, 3233442989u,
+ /* 128 -- */ 3988292384u, 2596254646u, 62317068u, 1957810842u,
+ /* 132 -- */ 3939845945u, 2647816111u, 81470997u, 1943803523u,
+ /* 136 -- */ 3814918930u, 2489596804u, 225274430u, 2053790376u,
+ /* 140 -- */ 3826175755u, 2466906013u, 167816743u, 2097651377u,
+ /* 144 -- */ 4027552580u, 2265490386u, 503444072u, 1762050814u,
+ /* 148 -- */ 4150417245u, 2154129355u, 426522225u, 1852507879u,
+ /* 152 -- */ 4275313526u, 2312317920u, 282753626u, 1742555852u,
+ /* 156 -- */ 4189708143u, 2394877945u, 397917763u, 1622183637u,
+ /* 160 -- */ 3604390888u, 2714866558u, 953729732u, 1340076626u,
+ /* 164 -- */ 3518719985u, 2797360999u, 1068828381u, 1219638859u,
+ /* 168 -- */ 3624741850u, 2936675148u, 906185462u, 1090812512u,
+ /* 172 -- */ 3747672003u, 2825379669u, 829329135u, 1181335161u,
+ /* 176 -- */ 3412177804u, 3160834842u, 628085408u, 1382605366u,
+ /* 180 -- */ 3423369109u, 3138078467u, 570562233u, 1426400815u,
+ /* 184 -- */ 3317316542u, 2998733608u, 733239954u, 1555261956u,
+ /* 188 -- */ 3268935591u, 3050360625u, 752459403u, 1541320221u,
+ /* 192 -- */ 2607071920u, 3965973030u, 1969922972u, 40735498u,
+ /* 196 -- */ 2617837225u, 3943577151u, 1913087877u, 83908371u,
+ /* 200 -- */ 2512341634u, 3803740692u, 2075208622u, 213261112u,
+ /* 204 -- */ 2463272603u, 3855990285u, 2094854071u, 198958881u,
+ /* 208 -- */ 2262029012u, 4057260610u, 1759359992u, 534414190u,
+ /* 212 -- */ 2176718541u, 4139329115u, 1873836001u, 414664567u,
+ /* 216 -- */ 2282248934u, 4279200368u, 1711684554u, 285281116u,
+ /* 220 -- */ 2405801727u, 4167216745u, 1634467795u, 376229701u,
+ /* 224 -- */ 2685067896u, 3608007406u, 1308918612u, 956543938u,
+ /* 228 -- */ 2808555105u, 3495958263u, 1231636301u, 1047427035u,
+ /* 232 -- */ 2932959818u, 3654703836u, 1088359270u, 936918000u,
+ /* 236 -- */ 2847714899u, 3736837829u, 1202900863u, 817233897u,
+ /* 240 -- */ 3183342108u, 3401237130u, 1404277552u, 615818150u,
+ /* 244 -- */ 3134207493u, 3453421203u, 1423857449u, 601450431u,
+ /* 248 -- */ 3009837614u, 3294710456u, 1567103746u, 711928724u,
+ /* 252 -- */ 3020668471u, 3272380065u, 1510334235u, 755167117u
+
+};
+
+/*
+ ======================================================================
+ Prototypes
+ ======================================================================
+*/
+
+static unsigned long ubootenv_crc32(unsigned char *, unsigned long);
+static int ubootenv_initialize(void);
+static void ubootenv_finalize(void);
+static int ubootenv_read(struct mtd_info *, size_t, void *);
+static void create_env_sysfs(void);
+/*
+ ======================================================================
+ ======================================================================
+*/
+
+/*
+ ----------------------------------------------------------------------
+ ubootenv_crc32
+*/
+
+static unsigned long
+ubootenv_crc32(unsigned char *start, unsigned long size)
+{
+ unsigned long crc = (unsigned long)0xffffffff, index;
+
+ DEBUG_PRINT("start=0x%lx size=0x%lx\n", (unsigned long)start, size);
+
+ for (index = 0; index < size; index++) {
+ unsigned long temp = (crc ^ *(start++)) & 0x000000ff;
+
+ crc = ((crc >> 8) & 0x00ffffff) ^ crc32_lut[temp];
+ }
+ return ~crc;
+}
+
+/*
+ ----------------------------------------------------------------------
+ ubootenv_read
+*/
+
+static int
+ubootenv_read(struct mtd_info *mtd, size_t size, void *buffer)
+{
+ int read = 0;
+ loff_t offset = 0;
+
+ DEBUG_PRINT("size=0x%x mtd->erasesize=0x%x mtd->size=0x%llx\n",
+ size, mtd->erasesize, mtd->size);
+
+ if (0 != size % mtd->erasesize) {
+ ERROR_PRINT("size=%u/%llu is not a multiple of erasesize=%u\n",
+ size, mtd->size, mtd->erasesize);
+ return -1;
+ }
+
+ if (size > mtd->size) {
+ ERROR_PRINT("size=%llu can't contain size=%u\n",
+ mtd->size, size);
+ return -1;
+ }
+
+ while ((read < size) && (offset < mtd->size)) {
+ int return_code;
+ size_t bytes_read;
+
+ DEBUG_PRINT("read=0x%x size=0x%x offset=0x%llx\n",
+ read, size, offset);
+
+ if (0 != mtd_block_isbad(mtd, offset)) {
+ offset += mtd->erasesize;
+ continue;
+ }
+
+ return_code = mtd_read(mtd, offset, mtd->erasesize,
+ &bytes_read, (u_char *) buffer);
+
+ if (mtd->erasesize != bytes_read) {
+ ERROR_PRINT("Error Reading Environment!\n");
+ return -1;
+ }
+
+ offset += mtd->erasesize;
+ read += mtd->erasesize;
+ buffer += mtd->erasesize;
+ }
+
+ return 0;
+}
+
+/*
+ ----------------------------------------------------------------------
+ ubootenv_initialize
+*/
+
+static int
+ubootenv_initialize(void)
+{
+ environment_t *env0;
+ environment_t *env1;
+ unsigned long crc32_env0;
+ unsigned long crc32_env1;
+ struct mtd_info *mtd_env0;
+ struct mtd_info *mtd_env1;
+
+ DEBUG_PRINT("Getting MTD Devices.\n");
+
+ mtd_env0 = get_mtd_device_nm("env-0");
+ if ((struct mtd_info *)-ENODEV == mtd_env0) {
+ ERROR_PRINT(" --> Couldn't get MTD device by name!\n");
+ return -1;
+ }
+
+ mtd_env1 = get_mtd_device_nm("env-1");
+ if ((struct mtd_info *)-ENODEV == mtd_env1) {
+ ERROR_PRINT(" --> Couldn't get MTD device by name!\n");
+ return -1;
+ }
+
+ /*
+ * If the erasesize is larger than the size of the environment,
+ * change the environment size (so reading and writing will
+ * work as expected) but use the original environment size to
+ * calculate the checksum.
+ */
+
+ if (mtd_env0->erasesize > uboot_env_size)
+ uboot_env_size = mtd_env0->erasesize;
+
+ DEBUG_PRINT("Allocating Environment Buffers.\n");
+
+ env0 = vmalloc(uboot_env_size);
+ if ((environment_t *)0 == env0) {
+ ERROR_PRINT("Unable to allocate %lu bytes\n", uboot_env_size);
+ return -1;
+ }
+
+ env1 = vmalloc(uboot_env_size);
+ if ((environment_t *) 0 == env1) {
+ ERROR_PRINT("Unable to allocate %lu bytes\n", uboot_env_size);
+ vfree((void *) env0);
+ return -1;
+ }
+
+ DEBUG_PRINT("Reading Environments.\n");
+
+ if (0 != ubootenv_read(mtd_env0, uboot_env_size, env0))
+ return -1;
+
+ if (0 != ubootenv_read(mtd_env1, uboot_env_size, env1))
+ return -1;
+
+ DEBUG_PRINT("Calculating CRC values.\n");
+ crc32_env0 = ubootenv_crc32((unsigned char *)env0->data,
+ ENVIRONMENT_DATA_SIZE(uboot_env_cs_size));
+ crc32_env1 = ubootenv_crc32((unsigned char *)env1->data,
+ ENVIRONMENT_DATA_SIZE(uboot_env_cs_size));
+ DEBUG_PRINT("crc32_env0=0x%lx env0->crc32=0x%lx\n",
+ crc32_env0, env0->crc32);
+ DEBUG_PRINT("crc32_env2=0x%lx env1->crc32=0x%lx\n",
+ crc32_env1, env1->crc32);
+ DEBUG_PRINT("Picking a Copy.\n");
+
+ if ((crc32_env0 == env0->crc32) &&
+ (crc32_env1 != env1->crc32)) {
+ /* Use env0 */
+ DEBUG_PRINT("Using Copy 0.\n");
+ uboot_env_current = 0;
+ vfree((void *) env1);
+ environment = env0;
+ } else if ((crc32_env0 != env0->crc32) &&
+ (crc32_env1 == env1->crc32)) {
+ /* Use env1 */
+ DEBUG_PRINT("Using Copy 1.\n");
+ uboot_env_current = 1;
+ vfree((void *) env0);
+ environment = env1;
+ } else if ((crc32_env0 != env0->crc32) &&
+ (crc32_env1 != env1->crc32)) {
+ /* No Environment Available */
+ uboot_env_current = -1;
+ vfree((void *) env0);
+ vfree((void *) env1);
+ ERROR_PRINT("Bad CRCs: No Valid U-Boot Environment Found!\n");
+ return -1;
+ } else if (env0->flags > env1->flags) {
+ /* Use env0 */
+ DEBUG_PRINT("Using Copy 0.\n");
+ uboot_env_current = 0;
+ vfree((void *) env1);
+ environment = env0;
+ } else if (env0->flags < env1->flags) {
+ /* Use env1 */
+ DEBUG_PRINT("Using Copy 1.\n");
+ uboot_env_current = 1;
+ vfree((void *) env0);
+ environment = env1;
+ } else if (env0->flags == env1->flags) {
+ /* Use Either */
+ DEBUG_PRINT("Using Copy 0.\n");
+ uboot_env_current = 0;
+ vfree((void *) env1);
+ environment = env0;
+ } else {
+ /* No Environment Available */
+ uboot_env_current = -1;
+ vfree((void *) env0);
+ vfree((void *) env1);
+ ERROR_PRINT("Bad Flags: No Valid U-Boot Environment Found!\n");
+ return -1;
+ }
+
+ DEBUG_PRINT("Done...\n");
+ create_env_sysfs();
+
+ return 0;
+}
+
+/*
+ ----------------------------------------------------------------------
+ ubootenv_finalize
+*/
+
+static void
+ubootenv_finalize(void)
+{
+ DEBUG_PRINT("Freeing the environment.\n");
+
+ if ((void *)0 != environment)
+ vfree((void *)environment);
+
+ environment = (environment_t *)0;
+}
+
+/*
+ ======================================================================
+ Public Interface
+ ======================================================================
+*/
+
+/*
+ ----------------------------------------------------------------------
+ ubootenv_get
+*/
+
+int
+ubootenv_get(const char *key, char *value)
+{
+ int return_code = -1;
+ char *string;
+
+ if (NULL == environment) {
+ ERROR_PRINT("Environment Isn't Available!\n");
+ return -1;
+ }
+
+ string = environment->data;
+
+ while (0x00 != string[0]) {
+ if (0 == strncmp(key, string, strlen(key))) {
+ char *value_ = strchr(string, '=');
+ ++value_;
+ strcpy(value, value_);
+ return_code = 0;
+ break;
+ }
+
+ string += (strlen(string) + 1);
+ }
+
+ return return_code;
+}
+EXPORT_SYMBOL(ubootenv_get);
+
+/*
+ ======================================================================
+ ======================================================================
+ Sysfs Stuff
+ ======================================================================
+ ======================================================================
+*/
+
+struct bin_attribute uboot_env[100];
+
+static ssize_t read_env(struct file *filep, struct kobject *kobj,
+ struct bin_attribute *bin_attr,
+ char *buf, loff_t off, size_t size)
+{
+ int retsize = -1;
+ char *string;
+
+ if (size <= 1)
+ return 0;
+
+ if (NULL == environment) {
+ ERROR_PRINT("Environment Isn't Available!\n");
+ return -1;
+ }
+
+ string = environment->data;
+
+ while (0x00 != string[0]) {
+ if (0 == strncmp(bin_attr->attr.name,
+ string, strlen(bin_attr->attr.name))) {
+ char *value_ = strchr(string, '=');
+ ++value_;
+
+ retsize = 1 + strlcpy(buf, value_, size);
+ break;
+ }
+
+ string += (strlen(string) + 1);
+ }
+
+ return retsize;
+}
+
+static void create_env_sysfs(void)
+{
+ char *string;
+ int i = 0;
+
+ if (NULL == environment) {
+ ERROR_PRINT("Environment Isn't Available!\n");
+ return;
+ }
+
+ string = environment->data;
+
+ while (0x00 != string[0]) {
+ char *value_ = strchr(string, '=');
+ char *name = vmalloc(1 + value_ - string);
+
+ strlcpy(name, string, 1 + value_ - string);
+
+ uboot_env[i].attr.name = name;
+ uboot_env[i].attr.mode = 0400;
+ uboot_env[i].size = strlen(string) - (value_ - string);
+ uboot_env[i].read = read_env;
+
+ if (sysfs_create_bin_file(ubootenv_kobj, &uboot_env[i]))
+ ERROR_PRINT("unable to add uboot-env sysfs file\n");
+
+ string += (strlen(string) + 1);
+ i++;
+ if (i > 99) {
+ ERROR_PRINT("More than 100 uboot env variables.\n");
+ return;
+ }
+ }
+}
+
+
+static ssize_t list_env(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ int i = 1;
+
+ while (i < uboot_env_size - 2) {
+ if (environment->data[i-1] == 0)
+ if (environment->data[i] == 0)
+ if (environment->data[i+1] == 0)
+ break;
+ i++;
+ }
+ memcpy(buf, environment->data, i);
+ return i;
+}
+
+static DEVICE_ATTR(list_env, 0444, list_env, NULL);
+
+static struct attribute *attrs[] = {
+ &dev_attr_list_env.attr,
+ NULL,
+};
+
+static struct attribute_group attr_group = {
+ .attrs = attrs,
+};
+
+
+/*
+ ======================================================================
+ ======================================================================
+ Linux Module Stuff
+ ======================================================================
+ ======================================================================
+*/
+
+/*
+ ----------------------------------------------------------------------
+ ubootenv_module_init
+*/
+
+int __init
+ubootenv_module_init(void)
+{
+ int retval;
+
+ DEBUG_PRINT("\n");
+ ubootenv_kobj = kobject_create_and_add("uboot-env", kernel_kobj);
+ if (!ubootenv_kobj)
+ return -ENOMEM;
+
+ /* Create the files associated with this kobject */
+ retval = sysfs_create_group(ubootenv_kobj, &attr_group);
+ if (retval)
+ goto fail;
+
+ retval = ubootenv_initialize();
+ if (retval)
+ goto fail;
+
+ return 0;
+fail:
+ kobject_put(ubootenv_kobj);
+
+ return retval;
+}
+
+module_init(ubootenv_module_init);
+
+/*
+ ----------------------------------------------------------------------
+ ubootenv_module_exit
+*/
+
+void __exit
+ubootenv_module_exit(void)
+{
+ DEBUG_PRINT("\n");
+ kobject_put(ubootenv_kobj);
+ ubootenv_finalize();
+}
+
+module_exit(ubootenv_module_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("John Jacques <john.jacques at lsi.com>");
+MODULE_DESCRIPTION("Read Access of the U-Boot Environment");
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 0f8ec3c..92d60d1 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -200,6 +200,7 @@ static inline int set_4byte(struct spi_nor *nor, struct flash_info *info,
static inline int spi_nor_sr_ready(struct spi_nor *nor)
{
int sr = read_sr(nor);
+
if (sr < 0)
return sr;
else
@@ -209,6 +210,7 @@ static inline int spi_nor_sr_ready(struct spi_nor *nor)
static inline int spi_nor_fsr_ready(struct spi_nor *nor)
{
int fsr = read_fsr(nor);
+
if (fsr < 0)
return fsr;
else
@@ -218,7 +220,9 @@ static inline int spi_nor_fsr_ready(struct spi_nor *nor)
static int spi_nor_ready(struct spi_nor *nor)
{
int sr, fsr;
+
sr = spi_nor_sr_ready(nor);
+
if (sr < 0)
return sr;
fsr = nor->flags & SNOR_F_USE_FSR ? spi_nor_fsr_ready(nor) : 1;
@@ -529,7 +533,7 @@ static const struct spi_device_id spi_nor_ids[] = {
{ "f25l32pa", INFO(0x8c2016, 0, 64 * 1024, 64, SECT_4K) },
/* Everspin */
- { "mr25h256", CAT25_INFO( 32 * 1024, 1, 256, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
+ { "mr25h256", CAT25_INFO(32 * 1024, 1, 256, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
{ "mr25h10", CAT25_INFO(128 * 1024, 1, 256, 3, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
/* Fujitsu */
@@ -585,7 +589,7 @@ static const struct spi_device_id spi_nor_ids[] = {
{ "s70fl01gs", INFO(0x010221, 0x4d00, 256 * 1024, 256, 0) },
{ "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) },
{ "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) },
- { "s25fl128s", INFO6(0x012018, 0x4d0180, 64 * 1024, 256, SPI_NOR_QUAD_READ) },
+ { "s25fl128s", INFO(0x012018, 0x4d0180, 64 * 1024, 256, SPI_NOR_QUAD_READ) },
{ "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64, 0) },
{ "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256, 0) },
{ "s25sl004a", INFO(0x010212, 0, 64 * 1024, 8, 0) },
@@ -663,10 +667,10 @@ static const struct spi_device_id spi_nor_ids[] = {
{ "w25q256", INFO(0xef4019, 0, 64 * 1024, 512, SECT_4K) },
/* Catalyst / On Semiconductor -- non-JEDEC */
- { "cat25c11", CAT25_INFO( 16, 8, 16, 1, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
- { "cat25c03", CAT25_INFO( 32, 8, 16, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
- { "cat25c09", CAT25_INFO( 128, 8, 32, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
- { "cat25c17", CAT25_INFO( 256, 8, 32, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
+ { "cat25c11", CAT25_INFO(16, 8, 16, 1, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
+ { "cat25c03", CAT25_INFO(32, 8, 16, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
+ { "cat25c09", CAT25_INFO(128, 8, 32, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
+ { "cat25c17", CAT25_INFO(256, 8, 32, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
{ "cat25128", CAT25_INFO(2048, 8, 64, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
{ },
};
@@ -943,6 +947,7 @@ int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode)
id = spi_nor_read_id(nor);
else
id = spi_nor_match_id(name);
+
if (IS_ERR_OR_NULL(id))
return -ENOENT;
diff --git a/include/linux/lsi_mtc_ioctl.h b/include/linux/lsi_mtc_ioctl.h
new file mode 100644
index 0000000..b8f8321
--- /dev/null
+++ b/include/linux/lsi_mtc_ioctl.h
@@ -0,0 +1,72 @@
+#ifndef __LSI_MTC_IOCTLH
+#define __LSI_MTC_IOCTLH
+
+#include <linux/ioctl.h>
+
+#define LSI_MTC_IOC_MAGIC 0x49
+
+struct lsi_mtc_cfg_t {
+ unsigned int opMode;
+ unsigned int recMode;
+ unsigned int clkMod;
+ unsigned int clkSpeed;
+ unsigned int buffMode;
+};
+
+
+
+struct lsi_mtc_tckclk_gate_t {
+ unsigned int gate_tck_test_logic_reset;
+ unsigned int gate_tck;
+};
+
+struct lsi_mtc_stats_regs_t {
+ unsigned int statsReg1;
+ unsigned int statsReg2;
+};
+
+
+struct lsi_mtc_debug_regs_t {
+ unsigned int debugReg0;
+ unsigned int debugReg1;
+ unsigned int debugReg2;
+ unsigned int debugReg3;
+ unsigned int debugReg4;
+ unsigned int debugReg5;
+};
+
+/* debug operation */
+#define MTC_DEBUG_OP _IOWR(LSI_MTC_IOC_MAGIC, 0, int)
+
+/* MTC configuration */
+#define MTC_CFG _IOW(LSI_MTC_IOC_MAGIC, 1, struct lsi_mtc_cfg_t)
+
+/* configure enable/disable single step */
+#define MTC_SINGLESTEP_ENABLE _IOW(LSI_MTC_IOC_MAGIC, 2, int)
+
+/*enale/disbale loop mode */
+#define MTC_LOOPMODE_ENABLE _IOW(LSI_MTC_IOC_MAGIC, 3, int)
+
+/* rest MTC */
+#define MTC_RESET _IO(LSI_MTC_IOC_MAGIC, 4)
+
+/* config gate tck clokc */
+#define MTC_TCKCLK_GATE _IOW(LSI_MTC_IOC_MAGIC, 5, struct lsi_mtc_tckclk_gate_t)
+
+
+/* start/stop execution */
+#define MTC_STARTSTOP_EXEC _IOW(LSI_MTC_IOC_MAGIC, 6, int)
+
+/* single step execution */
+#define MTC_SINGLESTEP_EXEC _IO(LSI_MTC_IOC_MAGIC, 7)
+
+/* continue after pause execution */
+#define MTC_CONTINUE_EXEC _IO(LSI_MTC_IOC_MAGIC, 8)
+
+/* read stats registers */
+#define MTC_READ_STATS _IOR(LSI_MTC_IOC_MAGIC, 9, struct lsi_mtc_stats_regs_t)
+
+/* read debug registers */
+#define MTC_READ_DEBUG _IOR(LSI_MTC_IOC_MAGIC, 10, struct lsi_mtc_debug_regs_t)
+
+#endif /* __LSI_MTC_IOCTLH*/
--
1.7.9.5
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