[linux-yocto] [PATCH 17/17] drivers/misc: Updates to the Axxia PEI Driver
Daniel Dragomir
daniel.dragomir at windriver.com
Tue May 16 11:39:09 PDT 2017
From: John Jacques <john.jacques at intel.com>
Add the ability, via a module parameter, to trace.
Fix incorrectly logic.
Update to match the new U-Boot PEI init code and parameters.
Signed-off-by: John Jacques <john.jacques at intel.com>
---
drivers/misc/axxia-pei.c | 188 +++++++++++++++++++++++------------------------
1 file changed, 94 insertions(+), 94 deletions(-)
diff --git a/drivers/misc/axxia-pei.c b/drivers/misc/axxia-pei.c
index bd65a90..21f0746 100644
--- a/drivers/misc/axxia-pei.c
+++ b/drivers/misc/axxia-pei.c
@@ -144,6 +144,34 @@ enum pipe_nphy {
four_phy = 0x3,
};
+static int pei_trace;
+module_param(pei_trace, int, S_IRUSR | S_IWUSR | S_IRGRP | S_IWGRP);
+MODULE_PARM_DESC(pei_trace, "enable pei_trace");
+
+static u32
+pei_readl(void *address)
+{
+ u32 value;
+
+ value = readl(address);
+
+ if (0 != pei_trace)
+ printk("PEI: Read 0x%x from 0x%px\n", value, address);
+
+ return value;
+}
+
+static void
+pei_writel(u32 value, void *address)
+{
+ writel(value, address);
+
+ if (0 != pei_trace)
+ printk("PEI: Wrote 0x%x to 0x%p\n", value, address);
+
+ return;
+}
+
/******************************************************************************
* PCIe/SRIO/SATA parameters
* Supported configs:
@@ -627,28 +655,29 @@ void disable_ltssm(enum PCIMode mode)
switch (mode) {
case PEI0:
/* LTSSM Disable for PEI0 */
- val = readl(pcie_gpreg0 + pcie_cc_gpreg_offset + 0x38);
+ val = pei_readl(pcie_gpreg0 + pcie_cc_gpreg_offset + 0x38);
val &= (~(0x1));
- writel(val, pcie_gpreg0 + pcie_cc_gpreg_offset + 0x38);
+ pei_writel(val, pcie_gpreg0 + pcie_cc_gpreg_offset + 0x38);
break;
case PEI1:
/* LTSSM Disable for PEI1 */
if (!is_5600)
break;
- val = readl(pcie_gpreg1 + pcie_cc_gpreg_offset + 0x38);
+ val = pei_readl(pcie_gpreg1 + pcie_cc_gpreg_offset + 0x38);
val &= (~(0x1));
- writel(val, pcie_gpreg1 + pcie_cc_gpreg_offset + 0x38);
+ pei_writel(val, pcie_gpreg1 + pcie_cc_gpreg_offset + 0x38);
break;
case PEI2:
/* LTSSM Disable for PEI2 */
if (!is_5600)
break;
- val = readl(pcie_gpreg2 + pcie_cc_gpreg_offset + 0x38);
+ val = pei_readl(pcie_gpreg2 + pcie_cc_gpreg_offset + 0x38);
val &= (~(0x1));
- writel(val, pcie_gpreg2 + pcie_cc_gpreg_offset + 0x38);
+ pei_writel(val, pcie_gpreg2 + pcie_cc_gpreg_offset + 0x38);
break;
default:
pr_err("%s Unsupported PEI %d\n", __func__, mode);
+ break;
};
mdelay(100); /* TODO: Why is this needed? */
@@ -1050,12 +1079,12 @@ update_settings(void)
Make sure the parameters are version 2...
*/
- if (0 != is_5500 || 0 == is_pei_control_v2)
+ if (is_5500 || !is_pei_control_v2)
return;
region = NCP_REGION_ID(0x115, 0);
- if (0 != is_5600)
+ if (is_5600)
number_of_serdes = 4;
else
number_of_serdes = 1;
@@ -1070,7 +1099,7 @@ update_settings(void)
unsigned int ref_range;
unsigned int value;
- if (0 != is_5600)
+ if (is_5600)
offset = (0xf8 + (i * 0x18));
else
offset = 0x44;
@@ -1148,12 +1177,12 @@ update_settings(void)
break;
}
- if (0 != is_5600)
+ if (is_5600)
offset = 0x18 + (i * 0x1c);
else
offset = 0xc + (i * 0x1c);
- if (0 != is_5600) {
+ if (is_5600) {
ncr_read32(region, offset, &value);
pr_debug("0x%x.0x%x.0x%x : 0x%x => ",
NCP_NODE_ID(region), NCP_TARGET_ID(region),
@@ -1179,9 +1208,9 @@ update_settings(void)
ncr_write32(region, offset, value);
}
+ return;
}
-
/*
------------------------------------------------------------------------------
pei_setup
@@ -1196,10 +1225,6 @@ pei_setup_56xx(unsigned int control)
unsigned int srio1_mode;
unsigned int srio0_speed;
unsigned int srio1_speed;
- unsigned int sata0_speed;
- unsigned int sata1_speed;
- unsigned int sata0_mode;
- unsigned int sata1_mode;
unsigned int srio0_ctrl;
unsigned int srio1_ctrl;
unsigned int pei0_mode;
@@ -1208,13 +1233,10 @@ pei_setup_56xx(unsigned int control)
u32 reg_val = 0;
int phy;
- pci_srio_sata_mode = (control & 0x03c00000) >> 22;
+ if (0 != pei_trace)
+ ncr_start_trace();
- sata0_mode = (control & 0x20) >> 5;
- sata1_mode = (control & 0x40) >> 6;
-
- sata0_speed = (control & 0xc0000) >> 18;
- sata1_speed = (control & 0x30000) >> 20;
+ pci_srio_sata_mode = (control & 0x03c00000) >> 22;
srio0_mode = (control & 0x8) >> 3;
srio1_mode = (control & 0x10) >> 4;
@@ -1248,11 +1270,12 @@ pei_setup_56xx(unsigned int control)
mdelay(100); /* TODO: Why is this needed? */
switch (pci_srio_sata_mode) {
-
case 1:
/*
- * PEI0x4 + PEI1x4
- */
+ PEI0x4 (HSS10-ch0,1; HSS11-ch0,1)
+ PEI1x4 (HSS12-ch0,1; HSS13-ch0,1)
+ */
+
set_sw_port_config0(pc0_PEI0x4);
set_sw_port_config1(pc1_PEI1x4);
set_pei0_rc_mode(rc_mode);
@@ -1266,20 +1289,21 @@ pei_setup_56xx(unsigned int control)
for (phy = 2; phy < 4; phy++)
release_reset(phy);
- /* Enable PEI0/PEI1 */
ncr_read32(NCP_REGION_ID(0x115, 0), 0x0, ®_val);
- reg_val |=
- (pei0_mode << 0) |
- (pei1_mode << 1);
+ reg_val |= (pei0_mode << 0) | (pei1_mode << 1);
ncr_write32(NCP_REGION_ID(0x115, 0), 0x0, reg_val);
break;
case 2:
/*
- * PEI0x2 + PEI2x2 + PEI1x2 + UNUSED (SATA0_SATA1)
- */
+ PEI0x2 (HSS10-ch0,1)
+ PEI2x2 (HSS11-ch0,1)
+ PEI1x2 (HSS12-ch0,1)
+ UNUSED (HSS13-ch0,1)
+ */
+
set_sw_port_config0(pc0_PEI0x2_PEI2x2);
- set_sw_port_config1(pc1_PEI1x2_SATA0x1_SATA1x1);
+ set_sw_port_config1(pc1_PEI1x2_PEI2x2);
set_pei0_rc_mode(rc_mode);
set_pipe_port_sel(pp_0_1_2_3);
@@ -1290,57 +1314,21 @@ pei_setup_56xx(unsigned int control)
if (pei2_mode)
release_reset(2);
- /* Enable PEI0/PEI1/PEI2 */
ncr_read32(NCP_REGION_ID(0x115, 0), 0, ®_val);
reg_val |= (pei0_mode << 0) | (pei1_mode << 1) |
(pei2_mode << 2);
ncr_write32(NCP_REGION_ID(0x115, 0), 0, reg_val);
-
-#if 0
- if (sata0_mode)
- setup_sata_mode(SATA0, sata0_speed);
- if (sata1_mode)
- setup_sata_mode(SATA1, sata1_speed);
- if (sata0_mode || sata1_mode) {
- release_reset(3);
- for (lane = 0; lane < 2; lane++) {
- if (!check_ack(3, lane, TX)) {
- pr_err("TX ACK not set for PHY3 LANE%d\n",
- lane);
- return 1;
- }
- if (!check_ack(3, lane, RX)) {
- pr_err("RX ACK not set for PHY3 LANE%d\n",
- lane);
- return 1;
- }
- }
- /* Set TX clock ready */
- set_tx_clk_ready();
- }
-
- /* Enable SATA0/SATA1 */
- ncr_read32(NCP_REGION_ID(0x115, 0), 0, ®_val);
- reg_val |= (sata0_mode << 29) | (sata1_mode << 30);
- ncr_write32(NCP_REGION_ID(0x115, 0), 0, reg_val);
-
- if (sata0_mode || sata1_mode) {
- if (!check_rx_valid(3, 0)) {
- pr_err("RX clock/data recovery not asserted for PHY3 LANE0\n");
- return 1;
- }
- if (!check_rx_valid(3, 1)) {
- pr_err("RX clock/data recovery not asserted for PHY3 LANE1\n");
- return 1;
- }
- }
-#endif
break;
-
case 3:
- /* PEI0x2 + SRIO0x2 + UNUSED (PEI1x2) + PEI2x2 */
- /* Enable PEI0/PEI2/SRIO0, PEI0 RC mode */
+ /*
+ * PEI0x2 (HSS10-ch0,1)
+ * SRIO0x2 (HSS11-ch0,1)
+ * UNUSED (HSS12-ch0,1)
+ * PEI2x2 (HSS13-ch0,1)
+ * INFO: Formerly case 6...
+ */
+
set_pei0_rc_mode(rc_mode);
set_sw_port_config0(pc0_PEI0x2_SRIO0x2);
set_sw_port_config1(pc1_PEI1x2_PEI2x2);
@@ -1349,12 +1337,15 @@ pei_setup_56xx(unsigned int control)
if (pei0_mode)
release_reset(0);
+ if (pei1_mode)
+ release_reset(2);
if (pei2_mode)
release_reset(3);
/* Enable PEI0/PEI1/PEI2 */
ncr_read32(NCP_REGION_ID(0x115, 0), 0, ®_val);
- reg_val |= (pei0_mode << 0) | (pei2_mode << 2);
+ reg_val |= (pei0_mode << 0) | (pei1_mode << 1) |
+ (pei2_mode << 2);
ncr_write32(NCP_REGION_ID(0x115, 0), 0, reg_val);
set_srio_mode(SRIO0, srio0_ctrl);
@@ -1383,23 +1374,28 @@ pei_setup_56xx(unsigned int control)
ncr_read32(NCP_REGION_ID(0x115, 0), 0, ®_val);
reg_val |= (srio0_mode << 3);
ncr_write32(NCP_REGION_ID(0x115, 0), 0, reg_val);
- pr_debug("Done\n");
break;
-
case 4:
- /* SRIO1x2 + SRIO0x2 + UNUSED(PEI1x2) + PEI2x2 */
- /* Enable PEI2/PEI1 */
+ /*
+ * SRIO1x2 (HSS10-ch0,1)
+ * SRIO0x2 (HSS11-ch0,1)
+ * UNUSED (HSS12-ch0,1)
+ * PEI2x2 (HSS13-ch0,1)
+ */
+
set_sw_port_config0(pc0_SRIO1x2_SRIO0x2);
set_sw_port_config1(pc1_PEI1x2_PEI2x2);
set_pipe_port_sel(pp_0_1_2_3);
+ if (pei1_mode)
+ release_reset(2);
if (pei2_mode)
release_reset(3);
/* Enable PEI1/PEI2 */
ncr_read32(NCP_REGION_ID(0x115, 0), 0, ®_val);
- reg_val |= (pei2_mode << 2);
+ reg_val |= (pei1_mode << 1) | (pei2_mode << 2);
ncr_write32(NCP_REGION_ID(0x115, 0), 0, reg_val);
set_srio_mode(SRIO0, srio0_ctrl);
@@ -1454,12 +1450,18 @@ pei_setup_56xx(unsigned int control)
pr_err("pei_setup control=0x%08x pci_srio_sata_mode=%d\n",
control, pci_srio_sata_mode);
- return -1;
- }
+ if (0 != pei_trace)
+ ncr_stop_trace();
+ return -1;
+ break;
+ }
update_settings();
+ if (0 != pei_trace)
+ ncr_stop_trace();
+
return 0;
}
@@ -1472,15 +1474,12 @@ pei_setup_67xx(unsigned int control)
u32 reg_val = 0;
pci_mode = (control & 0x00c00000) >> 22;
-
pei0_mode = (control & 0x1);
-
rc_mode = (control & 0x80) >> 7;
if (pei0_mode)
disable_ltssm(PEI0);
- /* enable serdes reset */
enable_reset(0);
/* Disable pei0 interfaces */
@@ -1495,9 +1494,11 @@ pei_setup_67xx(unsigned int control)
/*
* PEI0x2
*/
- set_pei0_rc_mode(rc_mode);
- set_pipe_port_sel(pp_0);
- set_pipe_nphy(one_phy);
+ if (0) {
+ set_pei0_rc_mode(rc_mode);
+ set_pipe_port_sel(pp_0);
+ set_pipe_nphy(one_phy);
+ }
if (pei0_mode)
release_reset(0);
@@ -1533,7 +1534,6 @@ pei_setup_67xx(unsigned int control)
return -1;
}
-
update_settings();
return 0;
@@ -1605,6 +1605,7 @@ int axxia_pei_setup(unsigned int control, unsigned int force)
not initialized the PEI. Start with that
assumption.
*/
+
if (0 == axxia_pei.initialized) {
if (is_5600)
rv = pei_setup_56xx(control);
@@ -1616,11 +1617,10 @@ int axxia_pei_setup(unsigned int control, unsigned int force)
ret = -EINVAL;
goto cleanup;
- } else {
+ } else
axxia_pei.initialized = 1;
- }
- msleep(100);
+ msleep(100);
}
cleanup:
--
2.7.4
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