[linux-yocto] [yocto-4.12][PATCH 1/3] x86/intel_rdt: Move special case code for Haswell to a quirk function

[Bruce Ashfield]

This series doesn't apply to the current 4.12:

-----------------
Applying: x86/intel_rdt: Move special case code for Haswell to a quirk 
function
error: patch failed: arch/x86/kernel/cpu/intel_rdt.c:172
error: arch/x86/kernel/cpu/intel_rdt.c: patch does not apply
Patch failed at 0001 x86/intel_rdt: Move special case code for Haswell 
to a quirk function
The copy of the patch that failed is found in:
    /home/bruce/poky-kernel/linux-yocto-4.12.git/.git/rebase-apply/patch
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".
---------------

Can you double check that the 4.12 you used to generate this series
matches what I have staged on git.yoctoproject.org.

Bruce

On 01/08/2018 10:20 PM, quanyang.wang at windriver.com wrote:
> From: Tony Luck <tony.luck at intel.com>
> 
> commit 0576113a387e0c8a5d9e24b4cd62605d1c9c0db8 upstream
> 
> No functional change, but lay the ground work for other per-model
> quirks.
> 
> Signed-off-by: Tony Luck <tony.luck at intel.com>
> Signed-off-by: Thomas Gleixner <tglx at linutronix.de>
> Cc: Fenghua" <fenghua.yu at intel.com>
> Cc: Ravi V" <ravi.v.shankar at intel.com>
> Cc: "Peter Zijlstra" <peterz at infradead.org>
> Cc: "Stephane Eranian" <eranian at google.com>
> Cc: "Andi Kleen" <ak at linux.intel.com>
> Cc: "David Carrillo-Cisneros" <davidcc at google.com>
> Cc: Vikas Shivappa <vikas.shivappa at linux.intel.com>
> Link: http://lkml.kernel.org/r/f195a83751b5f8b1d8a78bd3c1914300c8fa3142.1503512900.git.tony.luck@intel.com
> ---
>   arch/x86/kernel/cpu/intel_rdt.c | 52 ++++++++++++++++++++++-------------------
>   1 file changed, 28 insertions(+), 24 deletions(-)
> 
> diff --git a/arch/x86/kernel/cpu/intel_rdt.c b/arch/x86/kernel/cpu/intel_rdt.c
> index dfc7c48..5af2f8f 100644
> --- a/arch/x86/kernel/cpu/intel_rdt.c
> +++ b/arch/x86/kernel/cpu/intel_rdt.c
> @@ -172,34 +172,28 @@ static unsigned int cbm_idx(struct rdt_resource *r, unsigned int closid)
>    * is always 20 on hsw server parts. The minimum cache bitmask length
>    * allowed for HSW server is always 2 bits. Hardcode all of them.
>    */
> -static inline bool cache_alloc_hsw_probe(void)
> +static inline void cache_alloc_hsw_probe(void)
>   {
> -	if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
> -	    boot_cpu_data.x86 == 6 &&
> -	    boot_cpu_data.x86_model == INTEL_FAM6_HASWELL_X) {
> -		struct rdt_resource *r  = &rdt_resources_all[RDT_RESOURCE_L3];
> -		u32 l, h, max_cbm = BIT_MASK(20) - 1;
> +	struct rdt_resource *r  = &rdt_resources_all[RDT_RESOURCE_L3];
> +	u32 l, h, max_cbm = BIT_MASK(20) - 1;
>   
> -		if (wrmsr_safe(IA32_L3_CBM_BASE, max_cbm, 0))
> -			return false;
> -		rdmsr(IA32_L3_CBM_BASE, l, h);
> -
> -		/* If all the bits were set in MSR, return success */
> -		if (l != max_cbm)
> -			return false;
> +	if (wrmsr_safe(IA32_L3_CBM_BASE, max_cbm, 0))
> +		return;
> +	rdmsr(IA32_L3_CBM_BASE, l, h);
>   
> -		r->num_closid = 4;
> -		r->default_ctrl = max_cbm;
> -		r->cache.cbm_len = 20;
> -		r->cache.shareable_bits = 0xc0000;
> -		r->cache.min_cbm_bits = 2;
> -		r->alloc_capable = true;
> -		r->alloc_enabled = true;
> +	/* If all the bits were set in MSR, return success */
> +	if (l != max_cbm)
> +		return;
>   
> -		return true;
> -	}
> +	r->num_closid = 4;
> +	r->default_ctrl = max_cbm;
> +	r->cache.cbm_len = 20;
> +	r->cache.shareable_bits = 0xc0000;
> +	r->cache.min_cbm_bits = 2;
> +	r->alloc_capable = true;
> +	r->alloc_enabled = true;
>   
> -	return false;
> +	rdt_alloc_capable = true;
>   }
>   
>   /*
> @@ -648,7 +642,7 @@ static __init bool get_rdt_alloc_resources(void)
>   {
>   	bool ret = false;
>   
> -	if (cache_alloc_hsw_probe())
> +	if (rdt_alloc_capable)
>   		return true;
>   
>   	if (!boot_cpu_has(X86_FEATURE_RDT_A))
> @@ -690,8 +684,18 @@ static __init bool get_rdt_mon_resources(void)
>   	return !rdt_get_mon_l3_config(&rdt_resources_all[RDT_RESOURCE_L3]);
>   }
>   
> +static __init void rdt_quirks(void)
> +{
> +	switch (boot_cpu_data.x86_model) {
> +	case INTEL_FAM6_HASWELL_X:
> +		cache_alloc_hsw_probe();
> +		break;
> +	}
> +}
> +
>   static __init bool get_rdt_resources(void)
>   {
> +	rdt_quirks();
>   	rdt_alloc_capable = get_rdt_alloc_resources();
>   	rdt_mon_capable = get_rdt_mon_resources();
>   
>