[linux-yocto] [kernel v5.2/standard/xlnx-soc][PATCH 0/3] patches for zynq7000

[qwang2]

On 9/25/19 3:35 PM, Michal Simek wrote:
> On 25. 09. 19 8:18, qwang2 wrote:
>> On 9/25/19 1:34 PM, Michal Simek wrote:
>>> On 25. 09. 19 0:16, Bruce Ashfield wrote:
>>>> In message: [linux-yocto][kernel v5.2/standard/xlnx-soc][PATCH 0/3]
>>>> patches for zynq7000
>>>> on 23/09/2019 quanyang.wang at windriver.com wrote:
>>>>
>>>>> From: Quanyang Wang <quanyang.wang at windriver.com>
>>>>>
>>>>> Hi Bruce,
>>>>>
>>>>> Would you please help merge these patches to linux-yocto
>>>>> v5.2/standard/xlnx-soc branch?
>>>> These are now merged.
>>>>
>>>> Are these changes already done upstream, or applicable to upstream ?
>>>> I just
>>>> want to make sure we aren't only fixes these in the yocto kernel when
>>>> there
>>>> are other places that we can fix as well.
>>> We don't have this in mainline or xilinx kernel simply because none has
>>> asked for it.
>>> I am completely missing any manual/description how this should be tested
>>> but I expect this is based on mainline binding.
>> Hi Bruce & Michal,
>>
>> 1.  The patch "ARM: dts: zc702: Fix I2C bus warnings"  fix some dtb
>> building warnings. And
>>
>> this warnings will not happen in SDK (v4.19) and upstream. Because dtc
>> in SDK not check this
>>
>> and in upstream the zynq-zc702 dts file is in correct format. This patch
>> is needed only because I
>>
>> apply SDK patch to v5.2 kernel.
> I just need to take a look but not a problem with it at all.
>
>> 2. The patch "mmc: sdhci-of-arasan: Fix the incorrect soft reset
>> operation when runtime resuming"
>>
>> is also because that SDK patch use old function API and v5.2.16 use a
>> new one.
> ditto - it should be ok.
>
>> 3. The patch "arm: dts: zynq: enablement of coresight topology" is for
>> coresight. It is not mature now
>>
>> and I only simply verify it by using ptm2human, but will need more test
>> on this patch.
> Do you have any description somewhere how to use it? Or can you please
> put together any manual how to use it?

Hi Michal,

I just follow the document "Documentation/trace/coresight.txt" to test 
the coresight.

On target:

root at xilinx-zynq:/sys/bus/coresight/devices# echo 1 > 
f8801000.etb/enable_sink
root at xilinx-zynq:/sys/bus/coresight/devices# echo 1 > 
f889c000.ptm/enable_source
root at xilinx-zynq:/sys/bus/coresight/devices# sleep 2
root at xilinx-zynq:/sys/bus/coresight/devices# echo 0 > 
f889c000.ptm/enable_source
root at xilinx-zynq:/sys/bus/coresight/devices# dd if=/dev/f8801000.etb 
of=/root/1.bin
8+0 records in
8+0 records out
4096 bytes (4.1 kB, 4.0 KiB) copied, 0.00170529 s, 2.4 MB/s

On PC:

./ptm2human -p -i 1.bin > 1.txt

In 1.txt, I get some lines as below:

instruction addr at 0xffff0018, ARM state, exception (IRQ), secure state,
instruction addr at 0x80102160, ARM state,
instruction addr at 0x805ae280, ARM state,
instruction addr at 0x80177ac8, ARM state,
instruction addr at 0x80177ad8, ARM state,
instruction addr at 0x801893a8, ARM state,
instruction addr at 0x801881d8, ARM state,
instruction addr at 0x801893e8, ARM state,

I checked the System.map and the addresses like 0x80102160, 0x805ae280 
are for

__irq_svc and gic_handle_irq.  So these instructions which are captured 
should be in a irq call routine.

But ptm2human can't parse detailedly the tracing packets.

So I can't say that the coresight function works well with this patch. 
More test methods are needed to verify it.

In ./Documentation/trace/coresight.txt, it says that DS-5 and Trace32 
can also parse the

tracing packets and will get more detailed data as below:

Info                                    Tracing enabled
Instruction     106378866       0x8026B53C      E52DE004 false   
PUSH     {lr}
Instruction     0       0x8026B540      E24DD00C        false SUB      
sp,sp,#0xc
Instruction     0       0x8026B544      E3A03000        false MOV      r3,#0
Instruction     0       0x8026B548      E58D3004        false STR      
r3,[sp,#4]
Instruction     0       0x8026B54C      E59D3004        false LDR      
r3,[sp,#4]
Instruction     0       0x8026B550      E3530004        false CMP      r3,#4
Instruction     0       0x8026B554      E2833001        false ADD      
r3,r3,#1
Instruction     0       0x8026B558      E58D3004        false STR      
r3,[sp,#4]

But I am still striving to find out how to use DS-5 to parse the data.

Is there any plan for xilinx SDK to support coresight?

Thanks,

Quanyang

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