[linux-yocto] [kernel v5.2/standard/xlnx-soc][PATCH 2/3] arm: dts: zynq: enablement of coresight topology
qwang2
quanyang.wang at windriver.com
Thu Sep 26 06:35:02 PDT 2019
On 9/26/19 9:29 PM, Michal Simek wrote:
> On 26. 09. 19 15:17, qwang2 wrote:
>> On 9/26/19 8:50 PM, Michal Simek wrote:
>>> On 26. 09. 19 14:44, qwang2 wrote:
>>>> On 9/26/19 8:13 PM, Michal Simek wrote:
>>>>> On 26. 09. 19 14:05, qwang2 wrote:
>>>>>> On 9/26/19 7:11 PM, Michal Simek wrote:
>>>>>>> On 23. 09. 19 11:47, quanyang.wang at windriver.com wrote:
>>>>>>>> From: Zumeng Chen <zumeng.chen at windriver.com>
>>>>>>>>
>>>>>>>> This patch is to build the coresight topology structure of zynq-7000
>>>>>>>> series according to the docs of coresight and userguide of
>>>>>>>> zynq-7000.
>>>>>>>>
>>>>>>>> Signed-off-by: Zumeng Chen <zumeng.chen at windriver.com>
>>>>>>>> Signed-off-by: Quanyang Wang <quanyang.wang at windriver.com>
>>>>>>>> ---
>>>>>>>> arch/arm/boot/dts/zynq-7000.dtsi | 155
>>>>>>>> +++++++++++++++++++++++++++++++
>>>>>>>> 1 file changed, 155 insertions(+)
>>>>>>>>
>>>>>>>> diff --git a/arch/arm/boot/dts/zynq-7000.dtsi
>>>>>>>> b/arch/arm/boot/dts/zynq-7000.dtsi
>>>>>>>> index 07bd31d2ed4a..5602f4f3ad1c 100644
>>>>>>>> --- a/arch/arm/boot/dts/zynq-7000.dtsi
>>>>>>>> +++ b/arch/arm/boot/dts/zynq-7000.dtsi
>>>>>>>> @@ -419,5 +419,160 @@
>>>>>>>> reg = <0xf8005000 0x1000>;
>>>>>>>> timeout-sec = <10>;
>>>>>>>> };
>>>>>>>> +
>>>>>>>> + etb at f8801000 {
>>>>>>>> + compatible = "arm,coresight-etb10", "arm,primecell";
>>>>>>>> + reg = <0xf8801000 0x1000>;
>>>>>>>> + clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
>>>>>>>> + clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
>>>>>>>> +
>>>>>>>> + port {
>>>>>>>> + etb_in_port: endpoint {
>>>>>>>> + remote-endpoint = <&replicator_out_port1>;
>>>>>>>> + };
>>>>>>>> + };
>>>>>>>> + };
>>>>>>>> +
>>>>>>>> + tpiu at f8803000 {
>>>>>>>> + compatible = "arm,coresight-tpiu", "arm,primecell";
>>>>>>>> + reg = <0xf8803000 0x1000>;
>>>>>>>> + clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
>>>>>>>> + clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
>>>>>>>> +
>>>>>>>> + port {
>>>>>>>> + tpiu_in_port: endpoint {
>>>>>>>> + slave-mode;
>>>>>>>> + remote-endpoint = <&replicator_out_port0>;
>>>>>>>> + };
>>>>>>>> + };
>>>>>>>> + };
>>>>>>>> +
>>>>>>>> + funnel at 0,f8804000 {
>>>>>>>> + compatible = "arm,coresight-funnel", "arm,primecell";
>>>>>>>> + reg = <0xf8804000 0x1000>;
>>>>>>>> + clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
>>>>>>>> + clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
>>>>>>>> +
>>>>>>>> + /* funnel output ports */
>>>>>>>> + out-ports {
>>>>>>>> + port {
>>>>>>>> + funnel_out_port: endpoint {
>>>>>>>> + remote-endpoint =
>>>>>>>> + <&replicator_in_port0>;
>>>>>>>> + };
>>>>>>>> + };
>>>>>>>> + };
>>>>>>>> +
>>>>>>>> + in-ports {
>>>>>>>> + #address-cells = <1>;
>>>>>>>> + #size-cells = <0>;
>>>>>>>> +
>>>>>>>> + /* funnel input ports */
>>>>>>>> + port at 0 {
>>>>>>>> + reg = <0>;
>>>>>>>> + funnel0_in_port0: endpoint {
>>>>>>>> + slave-mode;
>>>>>>>> + remote-endpoint = <&ptm0_out_port>;
>>>>>>>> + };
>>>>>>>> + };
>>>>>>>> +
>>>>>>>> + port at 1 {
>>>>>>>> + reg = <1>;
>>>>>>>> + funnel0_in_port1: endpoint {
>>>>>>>> + slave-mode;
>>>>>>>> + remote-endpoint = <&ptm1_out_port>;
>>>>>>>> + };
>>>>>>>> + };
>>>>>>>> +
>>>>>>>> + port at 2 {
>>>>>>>> + reg = <2>;
>>>>>>>> + funnel0_in_port2: endpoint {
>>>>>>>> + slave-mode;
>>>>>>>> + };
>>>>>>>> + };
>>>>>>>> +
>>>>>>>> + port at 3 {
>>>>>>>> + reg = <3>;
>>>>>>>> + funnel0_in_port3: endpoint {
>>>>>>>> + slave-mode;
>>>>>>>> + remote-endpoint = <&itm_out_port>;
>>>>>>>> + };
>>>>>>>> + };
>>>>>>>> + /*The other input ports are not connect to
>>>>>>>> anything */
>>>>>>>> + };
>>>>>>>> + };
>>>>>>>> +
>>>>>>>> + replicator {
>>>>>>>> + compatible = "arm,coresight-replicator";
>>>>>>>> + clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
>>>>>>>> + clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
>>>>>>>> +
>>>>>>>> + out-ports {
>>>>>>>> + #address-cells = <1>;
>>>>>>>> + #size-cells = <0>;
>>>>>>>> +
>>>>>>>> + /* replicator output ports */
>>>>>>>> + port at 0 {
>>>>>>>> + reg = <0>;
>>>>>>>> + replicator_out_port0: endpoint {
>>>>>>>> + remote-endpoint = <&tpiu_in_port>;
>>>>>>>> + };
>>>>>>>> + };
>>>>>>>> + port at 1 {
>>>>>>>> + reg = <1>;
>>>>>>>> + replicator_out_port1: endpoint {
>>>>>>>> + remote-endpoint = <&etb_in_port>;
>>>>>>>> + };
>>>>>>>> + };
>>>>>>>> + };
>>>>>>>> + in-ports {
>>>>>>>> + /* replicator input port */
>>>>>>>> + port {
>>>>>>>> + replicator_in_port0: endpoint {
>>>>>>>> + slave-mode;
>>>>>>>> + remote-endpoint = <&funnel_out_port>;
>>>>>>>> + };
>>>>>>>> + };
>>>>>>>> + };
>>>>>>>> + };
>>>>>>>> +
>>>>>>>> + itm at 0,f8805000 {
>>>>>>>> + compatible = "arm,coresight-etm3x", "arm,primecell";
>>>>>>>> + reg = <0xf8805000 0x1000>;
>>>>>>>> + clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
>>>>>>>> + clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
>>>>>>>> +
>>>>>>>> + port {
>>>>>>>> + itm_out_port: endpoint {
>>>>>>>> + remote-endpoint = <&funnel0_in_port3>;
>>>>>>>> + };
>>>>>>>> + };
>>>>>>>> + };
>>>>>>>> +
>>>>>>>> + ptm at 0,f889c000 {
>>>>>>>> + compatible = "arm,coresight-etm3x", "arm,primecell";
>>>>>>>> + reg = <0xf889c000 0x1000>;
>>>>>>>> + clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
>>>>>>>> + clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
>>>>>>>> + cpu = <&cpu0>;
>>>>>>>> + port {
>>>>>>>> + ptm0_out_port: endpoint {
>>>>>>>> + remote-endpoint = <&funnel0_in_port0>;
>>>>>>>> + };
>>>>>>>> + };
>>>>>>>> + };
>>>>>>>> +
>>>>>>>> + ptm at 0,f889d000 {
>>>>>>>> + compatible = "arm,coresight-etm3x", "arm,primecell";
>>>>>>>> + reg = <0xf889d000 0x1000>;
>>>>>>>> + clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
>>>>>>>> + clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
>>>>>>>> + cpu = <&cpu1>;
>>>>>>>> + port {
>>>>>>>> + ptm1_out_port: endpoint {
>>>>>>>> + remote-endpoint = <&funnel0_in_port1>;
>>>>>>>> + };
>>>>>>>> + };
>>>>>>>> + };
>>>>>>>> };./arch/arm/boot/dts/hip04.dtsi
>>>>>>>> };
>>>>>>>>
>>>>>>> It is kind of interesting series. Especially in the context.
>>>>>>> In 1/3 you are fixing issues reported by latest dtc. And in 2/3
>>>>>>> you are
>>>>>>> introducing new one. :-)
>>>>>>> I think this should be fixed.
>>>>>> Hi Michal,
>>>>>>
>>>>>> I build the dtb files and not get any warning info. I can't find any
>>>>>> error.
>>>>>>
>>>>>> Would you please point it out?
>>>>> For example this node name "ptm at 0,f889d000"
>>>> Hi Michal,
>>>>
>>>> It should be "ptm at f889d000", I didn't notice that.
>>>>
>>>> Thank you for your advice. I will send a patch to fix them.
>>> I just tried to run it on mainline kernel and I think we need to do more
>>> changes.
>>>
>>> I see that binding is obsolete.
>>>
>>> coresight-dynamic-funnel f8804000.funnel: Uses OBSOLETE CoreSight funnel
>>> binding
>>> coresight-static-replicator amba:replicator: Uses OBSOLETE CoreSight
>>> replicator binding
>>>
>>> And then I can't see itm.
>>>
>>> root at Xilinx-ZC702-2014_4:/sys/bus/coresight/devices# ls
>>> etb0 etm0 etm1 funnel0 replicator0 tpiu0
>>>
>>> Are you able to probe it on your HW?
>> Yes, I have found these boot warnings at my side, I will update them
>> with new bindings.
>>
>> And ITM now is not supported in kernel. In
>> Documentation/trace/coresight.txt, it says:
>>
>> --
>>
>> As of this writing drivers for ITM, STMs and CTIs are not provided but are
>> expected to be added as the solution matures.
>> --
>>
>> So is it better to delete itm node from the dts file?
> I expect that dt binding for it hasn't been approved and I can't also
> see others SOCs to list it. It looks like that ITM shouldn't have etm
> compatible string too.
> At least comment is needed.
> I am ok with keep itm there but without etm compatible string. I expect
> that binding is not going to change there.
Hi Michal,
OK, got it.
Thanks,
Quanyang
>
> M
>
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