[meta-xilinx] zedboard usb issues
Simon Vincent
simon.vincent at xsilon.com
Wed Dec 3 01:21:12 PST 2014
I have fiddled around and got it working now.
Not 100% what fixed it but I added various items to the defconfig such as:
CONFIG_GPIOLIB=y
CONFIG_OF_GPIO=y
CONFIG_USB_ZYNQ=y
CONFIG_USB_ZYNQ_PHY=y
CONFIG_USB_ZYNQ_DR_OF=y
CONFIG_XILINX_VDMA=y
Thanks for the help.
Simon
On 03/12/14 01:01, Nathan Rossi wrote:
>> -----Original Message-----
>> From: Simon Vincent [mailto:simon.vincent at xsilon.com]
>> Sent: Tuesday, December 02, 2014 11:35 PM
>> To: Nathan Rossi
>> Cc: meta-xilinx at yoctoproject.org
>> Subject: Re: [meta-xilinx] zedboard usb issues
>>
>> I can get this to work using meta-xilinx/master using dizzy but I need to
>> get it working on the old daisy branch. I have pulled in the patch to
>> reset the usb phy via gpio but the usb does not work.
>>
>> I get the following in dmesg, yet the usb remains dead:
>> [ 1.156898] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
>> [ 1.163628] ehci-pci: EHCI PCI platform driver
>> [ 1.168697] ULPI transceiver vendor/product ID 0x0451/0x0007
>> [ 1.174317] ULPI integrity check: passed.
>> [ 1.179247] zynq-ehci zynq-ehci.0: Xilinx Zynq USB EHCI Host Controller
>> [ 1.186519] zynq-ehci zynq-ehci.0: new USB bus registered, assigned bus
>> number 1
>> [ 1.220201] zynq-ehci zynq-ehci.0: irq 53, io mem 0x00000000
>> [ 1.240182] zynq-ehci zynq-ehci.0: USB 2.0 started, EHCI 1.00
>> [ 1.252162] hub 1-0:1.0: USB hub found
>> [ 1.255999] hub 1-0:1.0: 1 port detected
>> [ 1.264821] usbcore: registered new interface driver usb-storage
>>
>> Any idea what else I need to pull into daisy?
> This appears like a power/link issue with the device connected, as it appears the host controller is probed and loaded including the root hub.
>
> Check a few things before digging into kernel config/dts issues:
>
> * Make sure the few jumpers for the USB phy are configured for host mode (JP2, JP3)
> * If you are not powering the usb devices via a powered hub, try using a powered hub
> * Make sure the usb micro B to host A cable you are using is not damaged
>
> Regards,
> Nathan
>
>> Thanks
>>
>> Simon
>>
>>
>> On 01/12/14 23:42, Nathan Rossi wrote:
>>
>>
>> -----Original Message-----
>> From: Simon Vincent [mailto:simon.vincent at xsilon.com]
>> Sent: Monday, December 01, 2014 8:27 PM
>> To: Nathan Rossi; Mike Looijmans; Philip Balister
>> Cc: meta-xilinx at yoctoproject.org
>> Subject: Re: [meta-xilinx] zedboard usb issues
>>
>> That makes a lot of sense.
>> I will give shorting R145 a go.
>> Thanks
>>
>>
>> Just a couple of things to note with shorting R145. You will need to
>> ensure the MIO 7 pin is always driven high when not resetting the PHY, as
>> there is a pull down on the "LD-MIO/VCFG" signal.
>>
>> Additionally to get the kernel to handle the reset/gpio you will
>> need to configure the device tree, and change the gpio defined, something
>> like this with meta-xilinx for example:
>>
>> --- a/conf/machine/boards/zedboard/zedboard-zynq7-board.dtsi
>> +++ b/conf/machine/boards/zedboard/zedboard-zynq7-board.dtsi
>> @@ -26,7 +26,7 @@
>> } ;
>> } ;
>> ps7_usb_0: ps7-usb at e0002000 {
>> - xlnx,phy-reset-gpio = <&ps7_gpio_0 85 0>;
>> + xlnx,phy-reset-gpio = <&ps7_gpio_0 7 0>;
>> } ;
>> ps7_qspi_0: ps7-qspi at e000d000 {
>> flash at 0 {
>>
>> Regards,
>> Nathan
>>
>>
>>
>> Simon
>>
>> On 27/11/14 04:55, Nathan Rossi wrote:
>>
>> Hi Simon,
>>
>> Unfortunately the Zedboard does not connect the PHY
>> reset pin to an MIO
>>
>> (unless you short R145, see the schematics for more details).
>> You will
>> need a bitstream that has the OTG-RESETN signal (pin G17)
>> hooked upto a
>> EMIO or a GPIO controller in PL. Sorry for confusion there, I
>> did not even
>> realize this myself until double checking.
>>
>>
>> Also, you can build u-boot-spl with meta-xilinx (not
>> fsbl as of yet).
>>
>> Regards,
>> Nathan
>>
>>
>> -----Original Message-----
>> From: Simon Vincent
>> [mailto:simon.vincent at xsilon.com]
>> Sent: Thursday, November 27, 2014 12:40 AM
>> To: Nathan Rossi; Mike Looijmans; Philip Balister
>> Cc: meta-xilinx at yoctoproject.org
>> Subject: Re: [meta-xilinx] zedboard usb issues
>>
>> Correction. I am still having problems with this.
>>
>> If I build against nrossi/next branch and include
>> a system.bit it works
>> but if I don't include a system.bit it does not
>> work and fails with the
>> following error.
>> zynq-dr e0002000.ps7-usb: Unable to init USB phy,
>> missing?
>>
>> Any idea why this is happening?
>>
>> Is it possible to get yocto to build the fsbl?
>>
>> Thanks
>>
>> Simon
>>
>> On 06/11/14 12:12, Simon Vincent wrote:
>>
>> I did a build using the nrossi/next branch
>> and I can confirm the USB
>> now works.
>> Many thanks
>>
>> Simon
>>
>> On 04/11/14 09:45, Nathan Rossi wrote:
>>
>> -----Original Message-----
>> From: meta-xilinx-
>> bounces at yoctoproject.org [mailto:meta-xilinx-
>> bounces at yoctoproject.org] On
>> Behalf Of Mike Looijmans
>> Sent: Monday, November 03, 2014
>> 4:48 PM
>> To: meta-xilinx at yoctoproject.org
>> Subject: Re: [meta-xilinx]
>> zedboard usb issues
>>
>> On 10/31/2014 10:35 AM, Nathan
>> Rossi wrote:
>> Met vriendelijke groet / kind
>> regards,
>>
>> Mike Looijmans
>> System Expert
>>
>>
>> TOPIC Embedded Systems
>> Eindhovenseweg 32-C, NL-5683 KH
>> Best
>> Postbus 440, NL-5680 AK Best
>> Telefoon: (+31) (0) 499 33 69 79
>> Telefax: (+31) (0) 499 33 69 70
>> E-mail: mike.looijmans at topic.nl
>> Website: www.topic.nl
>>
>> Please consider the environment
>> before printing this e-mail
>>
>> Topic zoekt gedreven (embedded)
>> software specialisten!
>> http://topic.nl/vacatures/topic-
>> zoekt-software-engineers/
>>
>> -----Original Message-----
>>
>> From: meta-xilinx-
>> bounces at yoctoproject.org [mailto:meta-xilinx-
>>
>> bounces at yoctoproject.org] On Behalf Of Simon Vincent
>> Sent: Friday,
>> October 31, 2014 12:48 AM
>> To: meta-
>> xilinx at yoctoproject.org
>> Subject: [meta-
>> xilinx] zedboard usb issues
>>
>> I have build a
>> zedboard image using the latest xilinx-yocto but I
>>
>> am
>>
>> having problems with
>> the usb.
>>
>> I find that 50% of
>> the time I get an error initialising the usb
>>
>> phy:
>>
>> root at zedboard-
>> zynq7:~# dmesg|grep -i usb
>> [ 0.562406]
>> usbcore: registered new interface driver usbfs
>> [ 0.568243]
>> usbcore: registered new interface driver hub
>> [ 0.573986]
>> usbcore: registered new device driver usb
>> [ 1.314762]
>> ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI)
>>
>> Driver
>>
>> [ 1.329453] zynq-
>> dr e0002000.ps7-usb: Unable to init USB phy,
>>
>> missing?
>>
>> [ 1.336866]
>> usbcore: registered new interface driver usb-
>>
>> storage
>>
>> [ 1.461775]
>> usbcore: registered new interface driver usbhid
>> [ 1.469402]
>> usbhid: USB HID core driver
>>
>> The rest of the time
>> I get the following but no usb devices are
>> recognised:
>>
>> root at zedboard-
>> zynq7:~# dmesg|grep -i usb
>> [ 0.562418]
>> usbcore: registered new interface driver usbfs
>> [ 0.568255]
>> usbcore: registered new interface driver hub
>> [ 0.573981]
>> usbcore: registered new device driver usb
>> [ 1.314193]
>> ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI)
>>
>> Driver
>>
>> [ 1.331922] Found
>> TI TUSB1210 ULPI transceiver.
>> [ 1.341299] zynq-
>> ehci zynq-ehci.0: Xilinx Zynq USB EHCI Host
>>
>> Controller
>>
>> [ 1.348773] zynq-
>> ehci zynq-ehci.0: new USB bus registered,
>> assigned
>> bus number 1
>> [ 1.405684] zynq-
>> ehci zynq-ehci.0: USB 2.0 started, EHCI 1.00
>> [ 1.418015] hub
>> 1-0:1.0: USB hub found
>> [ 1.429784]
>> usbcore: registered new interface driver usb-
>>
>> storage
>>
>> [ 1.560122]
>> usbcore: registered new interface driver usbhid
>> [ 1.567687]
>> usbhid: USB HID core driver
>>
>> If I boot using the
>> sdcard image that came with the zedboard the
>>
>> USB
>>
>> works every time and
>> recognises usb devices.
>>
>> Has anyone else had
>> problems with this?
>>
>> I have seen this before
>> with other boards. It is caused when the
>> USB PHY
>>
>> is not reset properly. I don't
>> see the issue in my testing most
>> likely due
>> to FSBL and or U-Boot resetting
>> the phy.
>>
>> I have been using a patch for
>> that for a while (the PHY reset in
>> FSBL only
>> worked for half the MIO pins). I
>> was waiting for the VBUS patch to
>> make it
>> to
>> Xilinx master-next before
>> submitting that to Xilinx. There's also
>> one in
>> the
>> ADI tree, but it uses much too
>> loose timings for the reset pulse.
>>
>> You can see my code here, this
>> solved the PHY reset on all boards:
>> https://github.com/topic-
>> embedded-
>>
>> products/linux/commit/7fb825c883e744c069a049ca4629c4664d2081af
>>
>> This is what I was referring to
>> regarding the kernel being able to
>> reset the PHY. But as it turns out the
>> linux-xlnx kernel only had
>> this in the xlnx_3.8 tree
>> (https://github.com/Xilinx/linux-
>>
>>
>> xlnx/commit/53e868300ad63c52137f47fd762a660071f1fd4e),
>>
>> and the patch was never merged with
>> the newer branches.
>>
>> That patch looks good Mike, I have
>> ported that change as a patch for
>> the linux-xlnx_3.14 recipe. I have
>> that on the nrossi/next branch,
>> which I intend to merge by the end of
>> the week.
>>
>> @Simon: I have also resolved that
>> toolchain error you were getting
>> with the newer meta-xilinx with dizzy.
>>
>> Regards,
>> Nathan
>>
>>
>>
>>
>> Linux is able to reset the
>> PHY, and I have a patch on my
>>
>> nrossi/next
>>
>> branch which should fix this
>> issue you are seeing. Would you be able
>>
>> to
>>
>> give it a try and let me know
>> the outcome?, the branch is at:
>>
>>
>> https://github.com/nathanrossi/meta-xilinx/compare/nrossi/next
>>
>> --
>>
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>>
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>>
>>
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