[meta-xilinx] meta-zynq

[Edward Vidal]

Hello
This is what I am seeing as the WORKDIR
cd
~/POKY/zynq_oe/build/tmp-eglibc/work/zedboard-oe-linux-gnueabi/fpga-image/5.AUTOINC-0a90b0d42e-r0/
Shouldn't the WORKDIR be two levels down in
~/POKY/zynq_oe/build/tmp-eglibc/work/zedboard-oe-linux-gnueabi/fpga-image/5.AUTOINC-0a90b0d42e-r0/git/cf_adv7511_zed?

MACHINE=zedboard bitbake my-image run.do_compile.3248 before the manual
steps below.
MACHINE=zedboard bitbake my-image run.do_compile.27899 after the manual
steps below.
These files are at https://github.com/develone/meta-zynq/tree/kernel-3.12
These steps are done manually to check if the Xilinx Tools are okay,
It appears that they are working since I get a file
ls -la
~/POKY/zynq_oe/build/tmp-eglibc/work/zedboard-oe-linux-gnueabi/fpga-image/5.AUTOINC-0a90b0d42e-r0/fpga.bin

-rw-rw-r-- 1 vidal vidal 4045564 Jan 17 06:40
/home/vidal/POKY/zynq_oe/build/tmp-eglibc/work/zedboard-oe-linux-gnueabi/fpga-image/5.AUTOINC-0a90b0d42e-r0/fpga.bin

Any and all help is appreciated.
Thanks
*****************Manual Steps and output*************************
source /opt/Xilinx/14.4/ISE_DS/settings64.sh
. /opt/Xilinx/14.4/ISE_DS/common/.settings64.sh
/opt/Xilinx/14.4/ISE_DS/common
. /opt/Xilinx/14.4/ISE_DS/EDK/.settings64.sh /opt/Xilinx/14.4/ISE_DS/EDK
. /opt/Xilinx/14.4/ISE_DS/common/CodeSourcery/.settings64.sh
/opt/Xilinx/14.4/ISE_DS/common/CodeSourcery
. /opt/Xilinx/14.4/ISE_DS/PlanAhead/.settings64.sh
/opt/Xilinx/14.4/ISE_DS/PlanAhead
. /opt/Xilinx/14.4/ISE_DS/../../Vivado/2012.4/.settings64.sh
/opt/Xilinx/14.4/ISE_DS/../../Vivado/2012.4
. /opt/Xilinx/14.4/ISE_DS/ISE/.settings64.sh /opt/Xilinx/14.4/ISE_DS/ISE
. /opt/Xilinx/14.4/ISE_DS/../../Vivado_HLS/2012.4/.settings64.sh
/opt/Xilinx/14.4/ISE_DS/../../Vivado_HLS/2012.4

xps -nw system.xmp
lots of output
Address Map for Processor processing_system7_0
  (0x41600000-0x4160ffff) axi_iic_0    axi_interconnect_1
  (0x41640000-0x4164ffff) axi_iic_1    axi_interconnect_1
  (0x43000000-0x4300ffff) axi_vdma_0    axi_interconnect_1
  (0x70e00000-0x70e0ffff) axi_hdmi_tx_16b_0    axi_interconnect_1
  (0x75c00000-0x75c0ffff) axi_spdif_tx_0    axi_interconnect_1
  (0x77600000-0x7760ffff) axi_i2s_adi_0    axi_interconnect_1
  (0x79000000-0x7900ffff) axi_clkgen_0    axi_interconnect_1

Checking platform address map ...

XPS%
run bits
gmake: Nothing to be done for `bits'.
0
run exporttosdk
gmake: Nothing to be done for `exporttosdk'.
0
exit
python
/home/vidal/POKY/zynq_oe/build/tmp-eglibc/work/zedboard-oe-linux-gnueabi/fpga-image/5.AUTOINC-0a90b0d42e-r0/fpga-bit-to-bin.py
--flip
/home/vidal/POKY/zynq_oe/build/tmp-eglibc/work/zedboard-oe-linux-gnueabi/fpga-image/5.AUTOINC-0a90b0d42e-r0/git/cf_adv7511_zed/implementation/system.bit
/home/vidal/POKY/zynq_oe/build/tmp-eglibc/work/zedboard-oe-linux-gnueabi/fpga-image/5.AUTOINC-0a90b0d42e-r0/fpga.bin
It appears that my xilinx tools are working since I get an fpga.bin file.
pwd
/home/vidal/POKY/zynq_oe/build/tmp-eglibc/work/zedboard-oe-linux-gnueabi/fpga-image/5.AUTOINC-0a90b0d42e-r0
vidal at ws009:~/POKY/zynq_oe/build/tmp-eglibc/work/zedboard-oe-linux-gnueabi/fpga-image/5.AUTOINC-0a90b0d42e-r0$
ls -la
total 3980
drwxrwxr-x  5 vidal vidal    4096 Jan 17 06:40 .
drwxrwxr-x  3 vidal vidal    4096 Jan 15 15:45 ..
-rw-rw-r--  1 vidal vidal 4045564 Jan 17 06:40 fpga.bin
-rwxr-xr-x  1 vidal vidal    1640 Jan 15 15:45 fpga-bit-to-bin.py
drwxr-xr-x 16 vidal vidal    4096 Jan 15 15:45 git
-rw-r--r--  1 vidal vidal     473 Jan 15 15:45 init
drwxrwxr-x  3 vidal vidal    4096 Jan 15 15:46 license-destdir
drwxrwxr-x  2 vidal vidal    4096 Jan 17 06:22 temp

*****************Manual Steps*************************
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