[meta-xilinx] meta-topic meta-zynq

[Edward Vidal]

Hello all,
This file was 644 /opt/Xilinx/14.4/ISE_DS/settings64.sh and works okay when
I manually source /opt/Xilinx/14.4/ISE_DS/settings64.sh.
I changed to 755 and the same error occurs.
-rwxr-xr-x   1 root root 1475 Jan  3 14:01 settings64.sh
The debug when MACHINE=zedboard bitbake my-image
This is vidal lic file location
| /home/vidal/.Xilinx/Xilinx.lic
| the LM_LICENSE_FILE variable is set base on XILINX_LM_LICENSE_FILE in the
local.conf
| /home/vidal/.Xilinx/Xilinx.lic
| Does does not appear at this point that the generate_bitstreams.sh is
going to be invoked
|  this is in the else
| this is the XILINX_TOOL_ARCH
| 64
| this is the WORKDIR
|
/home/vidal/POKY/zynq_oe/build/tmp-eglibc/work/zedboard-oe-linux-gnueabi/fpga-image/5.AUTOINC-0a90b0d42e-r0
| this is the Vivado path
| /opt/Xilinx/Vivado_HLS/2012.4
| this is the XILINX_TOOL_PATH
| /opt/Xilinx/14.4
| this is the iseprojf in the do loop after the if
| system.xmp
| this basename iseprojf .xmp in the if
| system
| this is the Vivado path
| /opt/Xilinx/Vivado_HLS/2012.4
| this is the XILINX_TOOL_ARCH
| 64
|  sourcing /opt/Xilinx/14.4/ISE_DS/settings64.sh after the
/opt/Xilinx/14.4 and 64 are extracted from local.conf
| this is the location of the error  as of 01/16/14
|
/home/vidal/POKY/zynq_oe/build/tmp-eglibc/work/zedboard-oe-linux-gnueabi/fpga-image/5.AUTOINC-0a90b0d42e-r0/temp/run.do_compile.19105:
143:
/home/vidal/POKY/zynq_oe/build/tmp-eglibc/work/zedboard-oe-linux-gnueabi/fpga-image/5.AUTOINC-0a90b0d42e-r0/temp/run.do_compile.19105:
source: not found
| WARNING: exit code 127 from a shell command.
| ERROR: Function failed: do_compile (log file is located at
/home/vidal/POKY/zynq_oe/build/tmp-eglibc/work/zedboard-oe-linux-gnueabi/fpga-image/5.AUTOINC-0a90b0d42e-r0/temp/log.do_compile.19105)
ERROR: Task 364 (/home/vidal/POKY/zynq_oe/meta-zynq/recipes-bsp/fpga/
fpga-image.bb, do_compile) failed with exit code '1'
Waiting for 2 running tasks to finish

local.conf variables
MACHINE ?= "zedboard"
ZYNQ_BOOTGEN = "bootgen"
#testing if these are the correct settings
#currently fpga-image is not working
XILINX_LM_LICENSE_FILE = "/home/vidal/.Xilinx/Xilinx.lic"
XILINX_TOOL_ARCH = "64"
BOARD_DESIGN_URI = "git://github.com/analogdevicesinc/fpgahdl_xilinx.git"
ZYNQ_BITFILE = "/home/vidal/zedboard_bit_files/system.bit"
XILINX_TOOL_PATH = "/opt/Xilinx/14.4"
XILINX_VIVADO_PATH = "/opt/Xilinx/Vivado_HLS/2012.4"
Manually do the following works okay.
source /opt/Xilinx/14.4/ISE_DS/settings64.sh
. /opt/Xilinx/14.4/ISE_DS/common/.settings64.sh
/opt/Xilinx/14.4/ISE_DS/common
. /opt/Xilinx/14.4/ISE_DS/EDK/.settings64.sh /opt/Xilinx/14.4/ISE_DS/EDK
. /opt/Xilinx/14.4/ISE_DS/common/CodeSourcery/.settings64.sh
/opt/Xilinx/14.4/ISE_DS/common/CodeSourcery
. /opt/Xilinx/14.4/ISE_DS/PlanAhead/.settings64.sh
/opt/Xilinx/14.4/ISE_DS/PlanAhead
. /opt/Xilinx/14.4/ISE_DS/../../Vivado/2012.4/.settings64.sh
/opt/Xilinx/14.4/ISE_DS/../../Vivado/2012.4
. /opt/Xilinx/14.4/ISE_DS/ISE/.settings64.sh /opt/Xilinx/14.4/ISE_DS/ISE
. /opt/Xilinx/14.4/ISE_DS/../../Vivado_HLS/2012.4/.settings64.sh
/opt/Xilinx/14.4/ISE_DS/../../Vivado_HLS/2012.4
Thanks
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