[meta-xilinx] system.bit and fpga.bin
Edward Vidal
vidal.develone at gmail.com
Mon Mar 31 10:56:40 PDT 2014
Hello,
Still trying to get slide switches and leds working, When the
/usr/share/fpga.bit is not present the system will not boot.
which GPIO are connected working version the leds were 61-68 and switches
were 69-76. What is the GPIO with fpga.bin?
Any and all help is appreciated,
Thanks
ZedBoard_Linux_Design system.ucf
############################
# #
# On-board LED's #
# #
############################
net processing_system7_0_GPIO<7> LOC = T22 | IOSTANDARD = LVCMOS33; #
LD0
net processing_system7_0_GPIO<8> LOC = T21 | IOSTANDARD = LVCMOS33; #
LD1
net processing_system7_0_GPIO<9> LOC = U22 | IOSTANDARD = LVCMOS33; #
LD2
net processing_system7_0_GPIO<10> LOC = U21 | IOSTANDARD = LVCMOS33; #
LD3
net processing_system7_0_GPIO<11> LOC = V22 | IOSTANDARD = LVCMOS33; #
LD4
net processing_system7_0_GPIO<12> LOC = W22 | IOSTANDARD = LVCMOS33; #
LD5
net processing_system7_0_GPIO<13> LOC = U19 | IOSTANDARD = LVCMOS33; #
LD6
net processing_system7_0_GPIO<14> LOC = U14 | IOSTANDARD = LVCMOS33; #
LD7
############################
# #
# On-board Slide Switches #
# #
############################
net processing_system7_0_GPIO<15> LOC = F22 | IOSTANDARD = LVCMOS33; #
SW0
net processing_system7_0_GPIO<16> LOC = G22 | IOSTANDARD = LVCMOS33; #
SW1
net processing_system7_0_GPIO<17> LOC = H22 | IOSTANDARD = LVCMOS33; #
SW2
net processing_system7_0_GPIO<18> LOC = F21 | IOSTANDARD = LVCMOS33; #
SW3
net processing_system7_0_GPIO<19> LOC = H19 | IOSTANDARD = LVCMOS33; #
SW4
net processing_system7_0_GPIO<20> LOC = H18 | IOSTANDARD = LVCMOS33; #
SW5
net processing_system7_0_GPIO<21> LOC = H17 | IOSTANDARD = LVCMOS33; #
SW6
net processing_system7_0_GPIO<22> LOC = M15 | IOSTANDARD = LVCMOS33; #
SW7
cf_adv7511_zed system.ucf
NET processing_system7_0_GPIO_pin[11] LOC = F22 |
IOSTANDARD="LVCMOS25"; # "SW0"
NET processing_system7_0_GPIO_pin[12] LOC = G22 |
IOSTANDARD="LVCMOS25"; # "SW1"
NET processing_system7_0_GPIO_pin[13] LOC = H22 |
IOSTANDARD="LVCMOS25"; # "SW2"
NET processing_system7_0_GPIO_pin[14] LOC = F21 |
IOSTANDARD="LVCMOS25"; # "SW3"
NET processing_system7_0_GPIO_pin[15] LOC = H19 |
IOSTANDARD="LVCMOS25"; # "SW4"
NET processing_system7_0_GPIO_pin[16] LOC = H18 |
IOSTANDARD="LVCMOS25"; # "SW5"
NET processing_system7_0_GPIO_pin[17] LOC = H17 |
IOSTANDARD="LVCMOS25"; # "SW6"
NET processing_system7_0_GPIO_pin[18] LOC = M15 |
IOSTANDARD="LVCMOS25"; # "SW7"
NET processing_system7_0_GPIO_pin[19] LOC = T22 |
IOSTANDARD="LVCMOS33"; # "LD0"
NET processing_system7_0_GPIO_pin[20] LOC = T21 |
IOSTANDARD="LVCMOS33"; # "LD1"
NET processing_system7_0_GPIO_pin[21] LOC = U22 |
IOSTANDARD="LVCMOS33"; # "LD2"
NET processing_system7_0_GPIO_pin[22] LOC = U21 |
IOSTANDARD="LVCMOS33"; # "LD3"
NET processing_system7_0_GPIO_pin[23] LOC = V22 |
IOSTANDARD="LVCMOS33"; # "LD4"
NET processing_system7_0_GPIO_pin[24] LOC = W22 |
IOSTANDARD="LVCMOS33"; # "LD5"
NET processing_system7_0_GPIO_pin[25] LOC = U19 |
IOSTANDARD="LVCMOS33"; # "LD6"
NET processing_system7_0_GPIO_pin[26] LOC = U14 |
IOSTANDARD="LVCMOS33"; # "LD7"
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