[meta-xilinx] Linux/bare-metal AMP interrupt routing

[Edward Wingate]

Nathan, once again, thanks.  That worked.

In the meantime, before getting your response, I set ICDIPTR15
register to 0x02000000 (route INT 63 to CPU1) and ICDICFR3 to
0x40000000 (configure INT 63 as high level active) at the start of my
CPU1 application:

(*(volatile uint32_t*)0xF8F0183C) = 0x02000000;
(*(volatile uint32_t*)0xF8F01C0C) = 0x40000000;

This worked as well.  I take it in my way, Linux doesn't even see the
interrupt?  In your way, does both CPU0 and CPU1 get INT 63?  Or does
CPU0 gets it and Linux forwards it to CPU1?  If the latter, what
mechanism does Linux use to forward the interrupt?



On Tue, Jun 9, 2015 at 10:45 AM, Nathan Rossi <nathan at nathanrossi.com> wrote:
> On Wed, Jun 10, 2015 at 3:27 AM, Edward Wingate <edwingate8 at gmail.com> wrote:
>> I got a bare-metal application running on CPU1 with Linux on CPU0,
>> using zynq_remoteproc as described in ug978.
>>
>> One thing I don't understand in ug978
>> (http://www.xilinx.com/support/documentation/sw_manuals/petalinux2014_2/ug978-petalinux-zynq-amp.pdf)
>> is the interrupts property in the remoteproc device tree entry, pg.
>> 23:
>>
>> test: remoteproc-test at 0 {
>>     compatible = "xlnx,zynq, remoteproc";
>>     reg = < 0x0 0x10000000 >;
>>     interrupt-parent = <&ps7_scugic_0>;
>>     interrupts = < 0 37 4 0 38 4 >;
>>     firmware = "freertos";
>>     ipino = <6>;
>>     vring0 = <2>;
>>     vring1 = <3>;
>> } ;
>>
>> It says "The interrupts property allows the consumption of interrupts
>> from Linux to be routed for FreeRTOS, in this case the TTC1 interrupts
>> are routed."  But 37 and 38 are XPS_PMU0_INT_ID and XPS_PMU1_INT_ID,
>> the performance monitoring units, not TTC1.  What am I missing here?
>>
>> I want to route FPGA2 interrupt (63) instead, so I have < 0 63 4 > for
>> interrupts property, but it doesn't seem to be working.  I set up the
>> interrupt handler on my CPU1 bare-metal application for
>> XPS_FPGA2_INT_ID, but it doesn't trigger.  Are there other config
>> items I need to change?
>
> So the trick is that the kernel maps the SGI or PPI (aka the first 32
> interrupts) separately to the Shared Peripheral Interrupts, so
> everything is shifted 32 interrupts down. e.g. TTC1's interrupt "69"
> is 69-32 = 37. So for interrupt 63 (as describe in the TRM) the
> interrupt number in the device tree is 31.
>
> For reference the first cell of the interrupts property describes
> whether it is SPI or SGI/PPI. Have a quick read of the GIC's binding
> doc: http://lxr.free-electrons.com/source/Documentation/devicetree/bindings/arm/gic.txt#L25
>
> Regards,
> Nathan
>
>>
>> Thanks for your help.
>> --
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