[meta-xilinx] 2nd ethernet port not detected

[Edward Wingate]

On Sat, Oct 24, 2015 at 1:57 PM, Eric Wong <ewong3 at gmail.com> wrote:
> We have an almost identical configuration to yours as you've been
> describing it and were able to get the 2nd ethernet port working by
> adding this to the sclr-clkc device tree:
> clocks = <&clkc 17>;
> clock-names = "gem1_emio_clk";
>
> It is working with both PHY addresses being 0, and the converter IP
> block has PHY address of 3. However, the PL converter IP block had to
> be configured to use an external clock with the FPGA2 clock feeding
> it.  The DT entry above will then allow the FPGA2 clock frequency to
> be set when eth1 interface is initialized. I don't know why an
> external clock had to be used vs. the default clock in that's already
> going to the converter IP block, but just couldn't get it to work with
> the default clock.

I finally got the hardware guys to try driving the GMII-to-RGMII IP
with an external clock and it's working now with your device tree
mods.  Thank you!