[meta-xilinx] 2nd ethernet port not detected

[Eric Wong]

> On Thu, Oct 15, 2015 at 20:56:46, Edward Wingate wrote:
>> On Thu, Oct 15, 2015 at 6:25 AM, Mike Looijmans <mike.looijmans at topic.nl> wrote:
>> As the datasheet should have explained, "0" is not a valid PHY address. So
>> that does not leave many options. "0" is actually the "broadcast" address on
>> the MDIO bus, so all phys will respond to it. Which makes it work with just
>> one PHY, but with multiple PHYs on the MDIO bus this will not work.
>
>The datasheet itself never mentions 0 as being the broadcast address.
>I wonder if the GMII-to_RGMII IP responds to 0, or only its assigned
>PHY address.

We have an almost identical configuration to yours as you've been
describing it and were able to get the 2nd ethernet port working by
adding this to the sclr-clkc device tree:
clocks = <&clkc 17>;
clock-names = "gem1_emio_clk";

It is working with both PHY addresses being 0, and the converter IP
block has PHY address of 3. However, the PL converter IP block had to
be configured to use an external clock with the FPGA2 clock feeding
it.  The DT entry above will then allow the FPGA2 clock frequency to
be set when eth1 interface is initialized. I don't know why an
external clock had to be used vs. the default clock in that's already
going to the converter IP block, but just couldn't get it to work with
the default clock.