[meta-xilinx] [PATCH] qemu_2.5%.bbappend: Create bbappend for arm64 patches
Nathan Rossi
nathan at nathanrossi.com
Fri Feb 26 05:11:48 PST 2016
Backport patches from post 4.5 QEMU which implement certain registers on
arm64 which are probed by newer kernels and are required in order to
boot newer (4.4+) kernels.
Signed-off-by: Nathan Rossi <nathan at nathanrossi.com>
---
.../4054bfa9e7986c9b7d2bf70f9e10af9647e376fc.patch | 90 ++++++++++++++++++++++
.../8a83ffc2dafad3499b87a736b17ab1b203fdb00b.patch | 37 +++++++++
.../978364f12adebb4b8d90fdeb71242cb3c1405740.patch | 49 ++++++++++++
recipes-zynqmp/qemu/qemu_4.5%.bbappend | 9 +++
4 files changed, 185 insertions(+)
create mode 100644 recipes-zynqmp/qemu/files/4054bfa9e7986c9b7d2bf70f9e10af9647e376fc.patch
create mode 100644 recipes-zynqmp/qemu/files/8a83ffc2dafad3499b87a736b17ab1b203fdb00b.patch
create mode 100644 recipes-zynqmp/qemu/files/978364f12adebb4b8d90fdeb71242cb3c1405740.patch
create mode 100644 recipes-zynqmp/qemu/qemu_4.5%.bbappend
diff --git a/recipes-zynqmp/qemu/files/4054bfa9e7986c9b7d2bf70f9e10af9647e376fc.patch b/recipes-zynqmp/qemu/files/4054bfa9e7986c9b7d2bf70f9e10af9647e376fc.patch
new file mode 100644
index 0000000..a8b4ffe
--- /dev/null
+++ b/recipes-zynqmp/qemu/files/4054bfa9e7986c9b7d2bf70f9e10af9647e376fc.patch
@@ -0,0 +1,90 @@
+From 4054bfa9e7986c9b7d2bf70f9e10af9647e376fc Mon Sep 17 00:00:00 2001
+From: Alistair Francis <alistair.francis at xilinx.com>
+Date: Thu, 18 Feb 2016 14:16:17 +0000
+Subject: [PATCH] target-arm: Add the pmceid0 and pmceid1 registers
+
+Signed-off-by: Aaron Lindsay <alindsay at codeaurora.org>
+Signed-off-by: Alistair Francis <alistair.francis at xilinx.com>
+Tested-by: Nathan Rossi <nathan at nathanrossi.com>
+Message-id: da0563119a9f56fd5fbdc26e7ed19a8a8457c5b9.1455060548.git.alistair.francis at xilinx.com
+[PMM: Use 0 for PMCEID0 values for A15 and A57 since our PMU
+ does not currently implement any events.]
+Reviewed-by: Peter Maydell <peter.maydell at linaro.org>
+Signed-off-by: Peter Maydell <peter.maydell at linaro.org>
+Upstream-Status: Backport
+---
+ target-arm/cpu-qom.h | 2 ++
+ target-arm/cpu.c | 2 ++
+ target-arm/cpu64.c | 2 ++
+ target-arm/helper.c | 16 ++++++++++++++++
+ 4 files changed, 22 insertions(+), 0 deletions(-)
+
+diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h
+index 07c0a71..1cc4502 100644
+--- a/target-arm/cpu-qom.h
++++ b/target-arm/cpu-qom.h
+@@ -148,6 +148,8 @@ typedef struct ARMCPU {
+ uint32_t id_pfr0;
+ uint32_t id_pfr1;
+ uint32_t id_dfr0;
++ uint32_t pmceid0;
++ uint32_t pmceid1;
+ uint32_t id_afr0;
+ uint32_t id_mmfr0;
+ uint32_t id_mmfr1;
+diff --git a/target-arm/cpu.c b/target-arm/cpu.c
+index f2393cd..e95b030 100644
+--- a/target-arm/cpu.c
++++ b/target-arm/cpu.c
+@@ -1156,6 +1156,8 @@ static void cortex_a15_initfn(Object *obj)
+ cpu->id_pfr0 = 0x00001131;
+ cpu->id_pfr1 = 0x00011011;
+ cpu->id_dfr0 = 0x02010555;
++ cpu->pmceid0 = 0x0000000;
++ cpu->pmceid1 = 0x00000000;
+ cpu->id_afr0 = 0x00000000;
+ cpu->id_mmfr0 = 0x10201105;
+ cpu->id_mmfr1 = 0x20000000;
+diff --git a/target-arm/cpu64.c b/target-arm/cpu64.c
+index c5bc19a..fa5eda2 100644
+--- a/target-arm/cpu64.c
++++ b/target-arm/cpu64.c
+@@ -135,6 +135,8 @@ static void aarch64_a57_initfn(Object *obj)
+ cpu->id_isar5 = 0x00011121;
+ cpu->id_aa64pfr0 = 0x00002222;
+ cpu->id_aa64dfr0 = 0x10305106;
++ cpu->pmceid0 = 0x00000000;
++ cpu->pmceid1 = 0x00000000;
+ cpu->id_aa64isar0 = 0x00011120;
+ cpu->id_aa64mmfr0 = 0x00001124;
+ cpu->dbgdidr = 0x3516d000;
+diff --git a/target-arm/helper.c b/target-arm/helper.c
+index a420a2a..6a4ec01 100644
+--- a/target-arm/helper.c
++++ b/target-arm/helper.c
+@@ -4380,6 +4380,22 @@ void register_cp_regs_for_features(ARMCPU *cpu)
+ .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 2,
+ .access = PL1_R, .type = ARM_CP_CONST,
+ .resetvalue = cpu->mvfr2 },
++ { .name = "PMCEID0", .state = ARM_CP_STATE_AA32,
++ .cp = 15, .opc1 = 0, .crn = 9, .crm = 12, .opc2 = 6,
++ .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
++ .resetvalue = cpu->pmceid0 },
++ { .name = "PMCEID0_EL0", .state = ARM_CP_STATE_AA64,
++ .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 6,
++ .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
++ .resetvalue = cpu->pmceid0 },
++ { .name = "PMCEID1", .state = ARM_CP_STATE_AA32,
++ .cp = 15, .opc1 = 0, .crn = 9, .crm = 12, .opc2 = 7,
++ .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
++ .resetvalue = cpu->pmceid1 },
++ { .name = "PMCEID1_EL0", .state = ARM_CP_STATE_AA64,
++ .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 7,
++ .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
++ .resetvalue = cpu->pmceid1 },
+ REGINFO_SENTINEL
+ };
+ /* RVBAR_EL1 is only implemented if EL1 is the highest EL */
+--
+1.7.0.4
+
diff --git a/recipes-zynqmp/qemu/files/8a83ffc2dafad3499b87a736b17ab1b203fdb00b.patch b/recipes-zynqmp/qemu/files/8a83ffc2dafad3499b87a736b17ab1b203fdb00b.patch
new file mode 100644
index 0000000..f5fb581
--- /dev/null
+++ b/recipes-zynqmp/qemu/files/8a83ffc2dafad3499b87a736b17ab1b203fdb00b.patch
@@ -0,0 +1,37 @@
+From 8a83ffc2dafad3499b87a736b17ab1b203fdb00b Mon Sep 17 00:00:00 2001
+From: Alistair Francis <alistair.francis at xilinx.com>
+Date: Thu, 18 Feb 2016 14:16:17 +0000
+Subject: [PATCH] target-arm: Add PMUSERENR_EL0 register
+
+The Linux kernel accesses this register early in its setup.
+
+Signed-off-by: Christopher Covington <christopher.covington at linaro.org>
+Signed-off-by: Alistair Francis <alistair.francis at xilinx.com>
+Reviewed-by: Peter Maydell <peter.maydell at linaro.org>
+Message-id: b30d536cb16ec57b4412172bb6dbc3f00d293e7d.1455060548.git.alistair.francis at xilinx.com
+Signed-off-by: Peter Maydell <peter.maydell at linaro.org>
+Upstream-Status: Backport
+---
+ target-arm/helper.c | 6 ++++++
+ 1 files changed, 6 insertions(+), 0 deletions(-)
+
+diff --git a/target-arm/helper.c b/target-arm/helper.c
+index 9e47f3d..5a0447b 100644
+--- a/target-arm/helper.c
++++ b/target-arm/helper.c
+@@ -1105,6 +1105,12 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
+ .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr),
+ .resetvalue = 0,
+ .writefn = pmuserenr_write, .raw_writefn = raw_write },
++ { .name = "PMUSERENR_EL0", .state = ARM_CP_STATE_AA64,
++ .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 14, .opc2 = 0,
++ .access = PL0_R | PL1_RW, .type = ARM_CP_ALIAS,
++ .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr),
++ .resetvalue = 0,
++ .writefn = pmuserenr_write, .raw_writefn = raw_write },
+ { .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1,
+ .access = PL1_RW,
+ .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
+--
+1.7.0.4
+
diff --git a/recipes-zynqmp/qemu/files/978364f12adebb4b8d90fdeb71242cb3c1405740.patch b/recipes-zynqmp/qemu/files/978364f12adebb4b8d90fdeb71242cb3c1405740.patch
new file mode 100644
index 0000000..8465dee
--- /dev/null
+++ b/recipes-zynqmp/qemu/files/978364f12adebb4b8d90fdeb71242cb3c1405740.patch
@@ -0,0 +1,49 @@
+From 978364f12adebb4b8d90fdeb71242cb3c1405740 Mon Sep 17 00:00:00 2001
+From: Alistair Francis <alistair.francis at xilinx.com>
+Date: Thu, 18 Feb 2016 14:16:17 +0000
+Subject: [PATCH] target-arm: Add the pmovsclr_el0 and pmintenclr_el1 registers
+
+Signed-off-by: Aaron Lindsay <alindsay at codeaurora.org>
+Signed-off-by: Alistair Francis <alistair.francis at xilinx.com>
+Tested-by: Nathan Rossi <nathan at nathanrossi.com>
+Reviewed-by: Peter Maydell <peter.maydell at linaro.org>
+Message-id: 50deeafb24958a5b6d7f594b5dda399a022c0e5b.1455060548.git.alistair.francis at xilinx.com
+Signed-off-by: Peter Maydell <peter.maydell at linaro.org>
+Upstream-Status: Backport
+---
+ target-arm/helper.c | 12 ++++++++++++
+ 1 files changed, 12 insertions(+), 0 deletions(-)
+
+diff --git a/target-arm/helper.c b/target-arm/helper.c
+index 6a4ec01..9e47f3d 100644
+--- a/target-arm/helper.c
++++ b/target-arm/helper.c
+@@ -1057,6 +1057,13 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
+ .accessfn = pmreg_access,
+ .writefn = pmovsr_write,
+ .raw_writefn = raw_write },
++ { .name = "PMOVSCLR_EL0", .state = ARM_CP_STATE_AA64,
++ .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 3,
++ .access = PL0_RW, .accessfn = pmreg_access,
++ .type = ARM_CP_ALIAS,
++ .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),
++ .writefn = pmovsr_write,
++ .raw_writefn = raw_write },
+ /* Unimplemented so WI. */
+ { .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4,
+ .access = PL0_W, .accessfn = pmreg_access, .type = ARM_CP_NOP },
+@@ -1107,6 +1114,11 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
+ .access = PL1_RW, .type = ARM_CP_ALIAS,
+ .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
+ .writefn = pmintenclr_write, },
++ { .name = "PMINTENCLR_EL1", .state = ARM_CP_STATE_AA64,
++ .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 2,
++ .access = PL1_RW, .type = ARM_CP_ALIAS,
++ .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
++ .writefn = pmintenclr_write },
+ { .name = "VBAR", .state = ARM_CP_STATE_BOTH,
+ .opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0,
+ .access = PL1_RW, .writefn = vbar_write,
+--
+1.7.0.4
+
diff --git a/recipes-zynqmp/qemu/qemu_4.5%.bbappend b/recipes-zynqmp/qemu/qemu_4.5%.bbappend
new file mode 100644
index 0000000..6f7cb50
--- /dev/null
+++ b/recipes-zynqmp/qemu/qemu_4.5%.bbappend
@@ -0,0 +1,9 @@
+
+FILESEXTRAPATHS_prepend := "${THISDIR}/files:"
+
+SRC_URI += " \
+ file://4054bfa9e7986c9b7d2bf70f9e10af9647e376fc.patch \
+ file://8a83ffc2dafad3499b87a736b17ab1b203fdb00b.patch \
+ file://978364f12adebb4b8d90fdeb71242cb3c1405740.patch \
+ "
+
--
2.7.0
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