[meta-xilinx] [PATCH v1] recipes-zynqmp: qemu: Update the backported patches

[Alistair Francis]

On Fri, May 13, 2016 at 2:32 AM, Nathan Rossi <nathan at nathanrossi.com> wrote:
> On Fri, May 13, 2016 at 3:07 AM, Alistair Francis
> <alistair.francis at xilinx.com> wrote:
>> The meta layer has updated QEMU to version 2.5.1 which includes a patch
>> that touches some of the target-arm code. This causes the backported
>> QEMU patch included in meta-xilinx to not apply.
>>
>> This patch updates the patch to apply to QEMU 2.5.1.
>
> Looks good, will apply once I branch krogoth as the 2.5.1 update is
> only in master.

Thanks Nathan!

I'm a little confused though, why can't you just apply it to master now?

Thanks,

Alistair

>
> Regards,
> Nathan
>
>>
>> Signed-off-by: Alistair Francis <alistair.francis at xilinx.com>
>> ---
>>  .../qemu/files/4054bfa9e7986c9b7d2bf70f9e10af9647e376fc.patch     | 8 ++++----
>>  1 file changed, 4 insertions(+), 4 deletions(-)
>>
>> diff --git a/recipes-zynqmp/qemu/files/4054bfa9e7986c9b7d2bf70f9e10af9647e376fc.patch b/recipes-zynqmp/qemu/files/4054bfa9e7986c9b7d2bf70f9e10af9647e376fc.patch
>> index a8b4ffe..50a17c4 100644
>> --- a/recipes-zynqmp/qemu/files/4054bfa9e7986c9b7d2bf70f9e10af9647e376fc.patch
>> +++ b/recipes-zynqmp/qemu/files/4054bfa9e7986c9b7d2bf70f9e10af9647e376fc.patch
>> @@ -1,4 +1,4 @@
>> -From 4054bfa9e7986c9b7d2bf70f9e10af9647e376fc Mon Sep 17 00:00:00 2001
>> +From 9b3c2f321954251e3eb0c908786d0b6953fe9f79 Mon Sep 17 00:00:00 2001
>>  From: Alistair Francis <alistair.francis at xilinx.com>
>>  Date: Thu, 18 Feb 2016 14:16:17 +0000
>>  Subject: [PATCH] target-arm: Add the pmceid0 and pmceid1 registers
>> @@ -62,10 +62,10 @@ diff --git a/target-arm/helper.c b/target-arm/helper.c
>>  index a420a2a..6a4ec01 100644
>>  --- a/target-arm/helper.c
>>  +++ b/target-arm/helper.c
>> -@@ -4380,6 +4380,22 @@ void register_cp_regs_for_features(ARMCPU *cpu)
>> -               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 2,
>> +@@ -4324,6 +4324,22 @@ void register_cp_regs_for_features(ARMCPU *cpu)
>> +               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 7,
>>                 .access = PL1_R, .type = ARM_CP_CONST,
>> -               .resetvalue = cpu->mvfr2 },
>> +               .resetvalue = 0 },
>>  +            { .name = "PMCEID0", .state = ARM_CP_STATE_AA32,
>>  +              .cp = 15, .opc1 = 0, .crn = 9, .crm = 12, .opc2 = 6,
>>  +              .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
>> --
>> 2.7.4
>>
> --
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