[meta-xilinx] Wrong DRAM set for custom board using FSBL + u-boot?

[Giordon Stark]

Hi Manju,

The generated device tree section (that I think is relevant) is here:
https://github.com/kratsg/meta-l1calo/blob/master/conf/machine/boards/gfex/prototype3/system-top.dts#L27-L30


memory {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>, <0x00000008 0x00000000 0x0 0x80000000>;
};

which I think looks correct and specifies from 0x0 -> 0x7FFFFFFF.

Giordon

On Wed, Dec 6, 2017 at 2:14 PM Manjukumar Harthikote Matha <
MANJUKUM at xilinx.com> wrote:

>
>
> > -----Original Message-----
> > From: meta-xilinx-bounces at yoctoproject.org [mailto:meta-xilinx-
> > bounces at yoctoproject.org] On Behalf Of Giordon Stark
> > Sent: Wednesday, December 06, 2017 9:26 AM
> > To: meta-xilinx at yoctoproject.org
> > Cc: Tang, Shaochun <stang at bnl.gov>
> > Subject: [meta-xilinx] Wrong DRAM set for custom board using FSBL +
> u-boot?
> >
> > Hi all,
> >
> > The board I'm using is defined here: https://github.com/kratsg/meta-
> > l1calo/blob/master/conf/machine/gfex-prototype3.conf but I'm noticing
> that the
> > DRAM reported by U-Boot is set to 4 GiB. This would be correct for
> ZCU102, but we
> > have 16 GiB DRAM for our custom (v3) board.
> >
> > Where is this setting configured? Is it part of the device tree? If so,
> why is the device-
> > tree-xlnx repository not exporting this correctly?
> >
>
> Does the device-tree generated indicate it as 16G?  If your HDF has
> correct settings for 16G, DTG should output correct fragment in the
> dts/dtsi files. You should compile the u-boot code with this dtb.
>
> > Thanks!
> >
> > Giordon
>
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