[meta-xilinx] Wrong DRAM set for custom board using FSBL + u-boot?

[Giordon Stark]

Hi Manju,

Indeed, you might be right... I guess now I'm confused by why Xilinx is not
exporting the HDF to a device tree correctly:

Our block design has the DDR set to 16gigs here:
https://www.dropbox.com/s/r8yzbvlf9kov8ei/Screenshot%202017-12-06%2018.40.29.png?dl=0

Our HDF indicates 2 banks:
https://www.dropbox.com/s/atodjbt6jf5b4aw/Screenshot%202017-12-06%2018.42.34.png?dl=0


The device tree right now seems to be saying:

bank1 @ 0x0 of size 0x80000000
bank2 @ 0x0 of size 0x80000000

I'm guessing the 1st and 3rd blocks here (size=0x0) could be safely
deleted. So I'm misunderstanding this. Is there a reason for this not to
match? A bug?

On Wed, Dec 6, 2017 at 6:32 PM Manjukumar Harthikote Matha <
MANJUKUM at xilinx.com> wrote:

>
>
> > -----Original Message-----
> > From: Giordon Stark [mailto:kratsg at gmail.com]
> > Sent: Wednesday, December 06, 2017 12:16 PM
> > To: Manjukumar Harthikote Matha <MANJUKUM at xilinx.com>
> > Cc: meta-xilinx at yoctoproject.org; Tang, Shaochun <stang at bnl.gov>
> > Subject: Re: [meta-xilinx] Wrong DRAM set for custom board using FSBL +
> u-boot?
> >
> > Hi Manju,
> >
> > The generated device tree section (that I think is relevant) is here:
> > https://github.com/kratsg/meta-
> >
> l1calo/blob/master/conf/machine/boards/gfex/prototype3/system-top.dts#L27-L30
> >
> > memory {
> > device_type = "memory";
> > reg = <0x0 0x0 0x0 0x80000000>, <0x00000008 0x00000000 0x0 0x80000000>;
> };
> >
> >
> Isn't this 4G? 2 banks for 2G each?
>
> Thanks,
> Manju
>
> > which I think looks correct and specifies from 0x0 -> 0x7FFFFFFF.
> >
> > Giordon
> >
> > On Wed, Dec 6, 2017 at 2:14 PM Manjukumar Harthikote Matha
> > <MANJUKUM at xilinx.com <mailto:MANJUKUM at xilinx.com> > wrote:
> >
> >
> >
> >
> >       > -----Original Message-----
> >       > From: meta-xilinx-bounces at yoctoproject.org <mailto:meta-xilinx-
> > bounces at yoctoproject.org>  [mailto:meta-xilinx- <mailto:meta-xilinx->
> >       > bounces at yoctoproject.org <mailto:bounces at yoctoproject.org> ] On
> > Behalf Of Giordon Stark
> >       > Sent: Wednesday, December 06, 2017 9:26 AM
> >       > To: meta-xilinx at yoctoproject.org <mailto:
> meta-xilinx at yoctoproject.org>
> >       > Cc: Tang, Shaochun <stang at bnl.gov <mailto:stang at bnl.gov> >
> >       > Subject: [meta-xilinx] Wrong DRAM set for custom board using
> FSBL + u-
> > boot?
> >       >
> >       > Hi all,
> >       >
> >       > The board I'm using is defined here:
> https://github.com/kratsg/meta-
> >       > l1calo/blob/master/conf/machine/gfex-prototype3.conf but I'm
> noticing
> > that the
> >       > DRAM reported by U-Boot is set to 4 GiB. This would be correct
> for
> > ZCU102, but we
> >       > have 16 GiB DRAM for our custom (v3) board.
> >       >
> >       > Where is this setting configured? Is it part of the device tree?
> If so, why is
> > the device-
> >       > tree-xlnx repository not exporting this correctly?
> >       >
> >
> >       Does the device-tree generated indicate it as 16G?  If your HDF
> has correct
> > settings for 16G, DTG should output correct fragment in the dts/dtsi
> files. You should
> > compile the u-boot code with this dtb.
> >
> >       > Thanks!
> >       >
> >       > Giordon
> >
>
>
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