[meta-xilinx] [meta-xilinx-bsp][PATCH 1/3] binutils: Rebase microblaze patches for binutils v2.30
Manjukumar Matha
manjukumar.harthikote-matha at xilinx.com
Mon May 21 17:59:42 PDT 2018
From: Alejandro Enedino Hernandez Samaniego <alejandr at xilinx.com>
oe-core has upgraded binutils to v2.30, which caused some of our patches
to fail, rebase these along with other minimal changes to avoid these
errors and provide compatibility with latest oe-core.
Signed-off-by: Alejandro Enedino Hernandez Samaniego <alejandr at xilinx.com>
Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha at xilinx.com>
---
.../recipes-microblaze/binutils/binutils%.bbappend | 2 +-
...Add-wdc.ext.clear-and-wdc.ext.flush-insns.patch | 67 ------
...-add-mlittle-endian-and-mbig-endian-flags.patch | 66 ------
...able-the-warning-message-for-eh_frame_hdr.patch | 36 ---
...laxation-of-assembler-resolved-references.patch | 78 -------
...Blaze-debug_loc-sections-after-linker-rel.patch | 236 --------------------
...Fix-bug-in-MicroBlaze-TLSTPREL-Relocation.patch | 37 ----
...MicroBlaze-address-extension-instructions.patch | 106 ---------
...Add-new-MicroBlaze-bit-field-instructions.patch | 232 --------------------
.../0009-Fixing-MicroBlaze-IMM-bug.patch | 31 ---
...n-GCC-so-that-it-will-support-.long-0U-an.patch | 36 ---
...ing-MicroBlaze-constant-range-check-issue.patch | 30 ---
...ze-fix-mask-for-barrel-shift-instructions.patch | 38 ----
...Add-wdc.ext.clear-and-wdc.ext.flush-insns.patch | 65 ++++++
...-add-mlittle-endian-and-mbig-endian-flags.patch | 64 ++++++
...able-the-warning-message-for-eh_frame_hdr.patch | 34 +++
...laxation-of-assembler-resolved-references.patch | 81 +++++++
...Blaze-debug_loc-sections-after-linker-rel.patch | 242 +++++++++++++++++++++
...Fix-bug-in-MicroBlaze-TLSTPREL-Relocation.patch | 35 +++
...MicroBlaze-address-extension-instructions.patch | 104 +++++++++
...Add-new-MicroBlaze-bit-field-instructions.patch | 232 ++++++++++++++++++++
.../0009-Fixing-MicroBlaze-IMM-bug.patch | 29 +++
...n-GCC-so-that-it-will-support-.long-0U-an.patch | 34 +++
...ing-MicroBlaze-constant-range-check-issue.patch | 28 +++
...ze-fix-mask-for-barrel-shift-instructions.patch | 36 +++
25 files changed, 985 insertions(+), 994 deletions(-)
delete mode 100644 meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.29/0001-MicroBlaze-Add-wdc.ext.clear-and-wdc.ext.flush-insns.patch
delete mode 100644 meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.29/0002-MicroBlaze-add-mlittle-endian-and-mbig-endian-flags.patch
delete mode 100644 meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.29/0003-Disable-the-warning-message-for-eh_frame_hdr.patch
delete mode 100644 meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.29/0004-Fix-relaxation-of-assembler-resolved-references.patch
delete mode 100644 meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.29/0005-Fixup-MicroBlaze-debug_loc-sections-after-linker-rel.patch
delete mode 100644 meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.29/0006-Fix-bug-in-MicroBlaze-TLSTPREL-Relocation.patch
delete mode 100644 meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.29/0007-Add-MicroBlaze-address-extension-instructions.patch
delete mode 100644 meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.29/0008-Add-new-MicroBlaze-bit-field-instructions.patch
delete mode 100644 meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.29/0009-Fixing-MicroBlaze-IMM-bug.patch
delete mode 100644 meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.29/0010-Fixed-bug-in-GCC-so-that-it-will-support-.long-0U-an.patch
delete mode 100644 meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.29/0011-Fixing-MicroBlaze-constant-range-check-issue.patch
delete mode 100644 meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.29/0012-MicroBlaze-fix-mask-for-barrel-shift-instructions.patch
create mode 100644 meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0001-MicroBlaze-Add-wdc.ext.clear-and-wdc.ext.flush-insns.patch
create mode 100644 meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0002-MicroBlaze-add-mlittle-endian-and-mbig-endian-flags.patch
create mode 100644 meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0003-Disable-the-warning-message-for-eh_frame_hdr.patch
create mode 100644 meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0004-Fix-relaxation-of-assembler-resolved-references.patch
create mode 100644 meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0005-Fixup-MicroBlaze-debug_loc-sections-after-linker-rel.patch
create mode 100644 meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0006-Fix-bug-in-MicroBlaze-TLSTPREL-Relocation.patch
create mode 100644 meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0007-Add-MicroBlaze-address-extension-instructions.patch
create mode 100644 meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0008-Add-new-MicroBlaze-bit-field-instructions.patch
create mode 100644 meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0009-Fixing-MicroBlaze-IMM-bug.patch
create mode 100644 meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0010-Fixed-bug-in-GCC-so-that-it-will-support-.long-0U-an.patch
create mode 100644 meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0011-Fixing-MicroBlaze-constant-range-check-issue.patch
create mode 100644 meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0012-MicroBlaze-fix-mask-for-barrel-shift-instructions.patch
diff --git a/meta-xilinx-bsp/recipes-microblaze/binutils/binutils%.bbappend b/meta-xilinx-bsp/recipes-microblaze/binutils/binutils%.bbappend
index 1784318..795c671 100644
--- a/meta-xilinx-bsp/recipes-microblaze/binutils/binutils%.bbappend
+++ b/meta-xilinx-bsp/recipes-microblaze/binutils/binutils%.bbappend
@@ -1,4 +1,4 @@
-FILESEXTRAPATHS_append_microblaze := "${THISDIR}/binutils-2.29:"
+FILESEXTRAPATHS_append_microblaze := "${THISDIR}/binutils-2.30:"
SRC_URI_append_microblaze = " \
file://0001-MicroBlaze-Add-wdc.ext.clear-and-wdc.ext.flush-insns.patch \
file://0002-MicroBlaze-add-mlittle-endian-and-mbig-endian-flags.patch \
diff --git a/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.29/0001-MicroBlaze-Add-wdc.ext.clear-and-wdc.ext.flush-insns.patch b/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.29/0001-MicroBlaze-Add-wdc.ext.clear-and-wdc.ext.flush-insns.patch
deleted file mode 100644
index 193061a..0000000
--- a/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.29/0001-MicroBlaze-Add-wdc.ext.clear-and-wdc.ext.flush-insns.patch
+++ /dev/null
@@ -1,67 +0,0 @@
-From d2979c539c309347493cebae91dc455fa3368f4f Mon Sep 17 00:00:00 2001
-From: David Holsgrove <david.holsgrove at xilinx.com>
-Date: Mon, 28 Aug 2017 19:53:52 -0700
-Subject: [PATCH] MicroBlaze Add wdc.ext.clear and wdc.ext.flush insns
-
-Added two new instructions, wdc.ext.clear and wdc.ext.flush,
-to enable MicroBlaze to flush an external cache, which is
-used with the new coherency support for multiprocessing.
-
-Signed-off-by: David Holsgrove <david.holsgrove at xilinx.com>
-Signed-off-by: Nagaraju Mekala <nagaraju.mekala at xilinx.com>
-Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha at xilinx.com>
-Upstream-Status: Pending
----
- opcodes/microblaze-opc.h | 5 ++++-
- opcodes/microblaze-opcm.h | 4 ++--
- 2 files changed, 6 insertions(+), 3 deletions(-)
-
-diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
-index 3954f927d1..b33178145f 100644
---- a/opcodes/microblaze-opc.h
-+++ b/opcodes/microblaze-opc.h
-@@ -91,6 +91,7 @@
- #define OPCODE_MASK_H3 0xFC000600 /* High 6 bits and bits 21, 22. */
- #define OPCODE_MASK_H32 0xFC00FC00 /* High 6 bits and bit 16-21. */
- #define OPCODE_MASK_H34B 0xFC0000FF /* High 6 bits and low 8 bits. */
-+#define OPCODE_MASK_H35B 0xFC0004FF /* High 6 bits and low 9 bits. */
- #define OPCODE_MASK_H34C 0xFC0007E0 /* High 6 bits and bits 21-26. */
-
- /* New Mask for msrset, msrclr insns. */
-@@ -101,7 +102,7 @@
- #define DELAY_SLOT 1
- #define NO_DELAY_SLOT 0
-
--#define MAX_OPCODES 289
-+#define MAX_OPCODES 291
-
- struct op_code_struct
- {
-@@ -174,7 +175,9 @@ struct op_code_struct
- {"wic", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000068, OPCODE_MASK_H34B, wic, special_inst },
- {"wdc", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000064, OPCODE_MASK_H34B, wdc, special_inst },
- {"wdc.clear", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000066, OPCODE_MASK_H34B, wdcclear, special_inst },
-+ {"wdc.ext.clear", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000466, OPCODE_MASK_H35B, wdcextclear, special_inst },
- {"wdc.flush", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000074, OPCODE_MASK_H34B, wdcflush, special_inst },
-+ {"wdc.ext.flush", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000476, OPCODE_MASK_H35B, wdcextflush, special_inst },
- {"mts", INST_TYPE_SPECIAL_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MTS, 0x9400C000, OPCODE_MASK_H13S, mts, special_inst },
- {"mfs", INST_TYPE_RD_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MFS, 0x94008000, OPCODE_MASK_H23S, mfs, special_inst },
- {"br", INST_TYPE_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98000000, OPCODE_MASK_H124, br, branch_inst },
-diff --git a/opcodes/microblaze-opcm.h b/opcodes/microblaze-opcm.h
-index 6b25173442..00dc131302 100644
---- a/opcodes/microblaze-opcm.h
-+++ b/opcodes/microblaze-opcm.h
-@@ -33,8 +33,8 @@ enum microblaze_instr
- /* 'or/and/xor' are C++ keywords. */
- microblaze_or, microblaze_and, microblaze_xor,
- andn, pcmpbf, pcmpbc, pcmpeq, pcmpne, sra, src, srl, sext8, sext16,
-- wic, wdc, wdcclear, wdcflush, mts, mfs, mbar, br, brd,
-- brld, bra, brad, brald, microblaze_brk, beq, beqd, bne, bned, blt,
-+ wic, wdc, wdcclear, wdcextclear, wdcflush, wdcextflush, mts, mfs, mbar, br,
-+ brd, brld, bra, brad, brald, microblaze_brk, beq, beqd, bne, bned, blt,
- bltd, ble, bled, bgt, bgtd, bge, bged, ori, andi, xori, andni,
- imm, rtsd, rtid, rtbd, rted, bri, brid, brlid, brai, braid, bralid,
- brki, beqi, beqid, bnei, bneid, blti, bltid, blei, bleid, bgti,
---
-2.15.0
-
diff --git a/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.29/0002-MicroBlaze-add-mlittle-endian-and-mbig-endian-flags.patch b/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.29/0002-MicroBlaze-add-mlittle-endian-and-mbig-endian-flags.patch
deleted file mode 100644
index c8142ca..0000000
--- a/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.29/0002-MicroBlaze-add-mlittle-endian-and-mbig-endian-flags.patch
+++ /dev/null
@@ -1,66 +0,0 @@
-From 90fa3cca5ce8ca19c9aca521bbc3d47485f02bf1 Mon Sep 17 00:00:00 2001
-From: Nagaraju Mekala <nagaraju.mekala at xilinx.com>
-Date: Mon, 28 Aug 2017 19:53:53 -0700
-Subject: [PATCH] MicroBlaze add mlittle-endian and mbig-endian flags
-
-Added support in gas for mlittle-endian and mbig-endian flags
-as options.
-
-Updated show usage for MicroBlaze specific assembler options
-to include new entries.
-
-Signed-off-by: Nagaraju Mekala <nagaraju.mekala at xilinx.com>
-Signed-off-by: David Holsgrove <david.holsgrove at xilinx.com>
-Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha at xilinx.com>
-Upstream-Status: Pending
----
- gas/config/tc-microblaze.c | 9 +++++++++
- 1 file changed, 9 insertions(+)
-
-diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
-index 0124422168..d47793646b 100644
---- a/gas/config/tc-microblaze.c
-+++ b/gas/config/tc-microblaze.c
-@@ -37,6 +37,8 @@
-
- #define OPTION_EB (OPTION_MD_BASE + 0)
- #define OPTION_EL (OPTION_MD_BASE + 1)
-+#define OPTION_LITTLE (OPTION_MD_BASE + 2)
-+#define OPTION_BIG (OPTION_MD_BASE + 3)
-
- void microblaze_generate_symbol (char *sym);
- static bfd_boolean check_spl_reg (unsigned *);
-@@ -1837,6 +1839,8 @@ struct option md_longopts[] =
- {
- {"EB", no_argument, NULL, OPTION_EB},
- {"EL", no_argument, NULL, OPTION_EL},
-+ {"mlittle-endian", no_argument, NULL, OPTION_LITTLE},
-+ {"mbig-endian", no_argument, NULL, OPTION_BIG},
- { NULL, no_argument, NULL, 0}
- };
-
-@@ -2471,9 +2475,11 @@ md_parse_option (int c, const char * arg ATTRIBUTE_UNUSED)
- switch (c)
- {
- case OPTION_EB:
-+ case OPTION_BIG:
- target_big_endian = 1;
- break;
- case OPTION_EL:
-+ case OPTION_LITTLE:
- target_big_endian = 0;
- break;
- default:
-@@ -2488,6 +2494,9 @@ md_show_usage (FILE * stream ATTRIBUTE_UNUSED)
- /* fprintf(stream, _("\
- MicroBlaze options:\n\
- -noSmall Data in the comm and data sections do not go into the small data section\n")); */
-+ fprintf (stream, _(" MicroBlaze specific assembler options:\n"));
-+ fprintf (stream, " -%-23s%s\n", "mbig-endian", N_("assemble for a big endian cpu"));
-+ fprintf (stream, " -%-23s%s\n", "mlittle-endian", N_("assemble for a little endian cpu"));
- }
-
-
---
-2.15.0
-
diff --git a/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.29/0003-Disable-the-warning-message-for-eh_frame_hdr.patch b/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.29/0003-Disable-the-warning-message-for-eh_frame_hdr.patch
deleted file mode 100644
index 55f4ce3..0000000
--- a/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.29/0003-Disable-the-warning-message-for-eh_frame_hdr.patch
+++ /dev/null
@@ -1,36 +0,0 @@
-From f81026057270346cfcfa16e460dcb04a9fa48511 Mon Sep 17 00:00:00 2001
-From: "Edgar E. Iglesias" <edgar.iglesias at gmail.com>
-Date: Mon, 28 Aug 2017 19:53:54 -0700
-Subject: [PATCH] Disable the warning message for eh_frame_hdr
-
-Signed-off-by: Edgar E. Iglesias <edgar.iglesias at gmail.com>
-Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha at xilinx.com>
-Upstream-Status: Inappropriate [workaround]
----
- bfd/elf-eh-frame.c | 9 ++++++---
- 1 file changed, 6 insertions(+), 3 deletions(-)
-
-diff --git a/bfd/elf-eh-frame.c b/bfd/elf-eh-frame.c
-index 52ba9c6213..7ac511dfcb 100644
---- a/bfd/elf-eh-frame.c
-+++ b/bfd/elf-eh-frame.c
-@@ -1046,10 +1046,13 @@ _bfd_elf_parse_eh_frame (bfd *abfd, struct bfd_link_info *info,
- goto success;
-
- free_no_table:
-- (*info->callbacks->einfo)
-+ /* FIXME: Remove the microblaze specifics when relaxing gets fixed. */
-+ if (bfd_get_arch(abfd) != bfd_arch_microblaze) {
- /* xgettext:c-format */
-- (_("%P: error in %B(%A); no .eh_frame_hdr table will be created.\n"),
-- abfd, sec);
-+ (*info->callbacks->einfo)
-+ (_("%P: error in %B(%A); no .eh_frame_hdr table will be created.\n"),
-+ abfd, sec);
-+ }
- hdr_info->u.dwarf.table = FALSE;
- if (sec_info)
- free (sec_info);
---
-2.15.0
-
diff --git a/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.29/0004-Fix-relaxation-of-assembler-resolved-references.patch b/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.29/0004-Fix-relaxation-of-assembler-resolved-references.patch
deleted file mode 100644
index c145a74..0000000
--- a/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.29/0004-Fix-relaxation-of-assembler-resolved-references.patch
+++ /dev/null
@@ -1,78 +0,0 @@
-From 0d5966951c379882b7557befaa229dc5def8dafe Mon Sep 17 00:00:00 2001
-From: "Edgar E. Iglesias" <edgar.iglesias at gmail.com>
-Date: Mon, 28 Aug 2017 19:53:55 -0700
-Subject: [PATCH] Fix relaxation of assembler resolved references
-
-Signed-off-by: Edgar E. Iglesias <edgar.iglesias at gmail.com>
-Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha at xilinx.com>
-Upstream-Status: Pending
----
- bfd/elf32-microblaze.c | 39 +++++++++++++++++++++++++++++++++++++++
- gas/config/tc-microblaze.c | 1 +
- 2 files changed, 40 insertions(+)
-
-diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c
-index 265773675c..c3dbead48d 100644
---- a/bfd/elf32-microblaze.c
-+++ b/bfd/elf32-microblaze.c
-@@ -1901,6 +1901,45 @@ microblaze_elf_relax_section (bfd *abfd,
- irelscanend = irelocs + o->reloc_count;
- for (irelscan = irelocs; irelscan < irelscanend; irelscan++)
- {
-+ if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_NONE)
-+ {
-+ unsigned int val;
-+
-+ isym = isymbuf + ELF32_R_SYM (irelscan->r_info);
-+
-+ /* This was a PC-relative instruction that was completely resolved. */
-+ if (ocontents == NULL)
-+ {
-+ if (elf_section_data (o)->this_hdr.contents != NULL)
-+ ocontents = elf_section_data (o)->this_hdr.contents;
-+ else
-+ {
-+ /* We always cache the section contents.
-+ Perhaps, if info->keep_memory is FALSE, we
-+ should free them, if we are permitted to. */
-+
-+ if (o->rawsize == 0)
-+ o->rawsize = o->size;
-+ ocontents = (bfd_byte *) bfd_malloc (o->rawsize);
-+ if (ocontents == NULL)
-+ goto error_return;
-+ if (!bfd_get_section_contents (abfd, o, ocontents,
-+ (file_ptr) 0,
-+ o->rawsize))
-+ goto error_return;
-+ elf_section_data (o)->this_hdr.contents = ocontents;
-+ }
-+ }
-+
-+ irelscan->r_addend -= calc_fixup (irelscan->r_addend
-+ + isym->st_value, sec);
-+ val = bfd_get_32 (abfd, ocontents + irelscan->r_offset);
-+ microblaze_bfd_write_imm_value_32 (abfd, ocontents + irelscan->r_offset,
-+ irelscan->r_addend);
-+ }
-+ if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_64_NONE) {
-+ fprintf(stderr, "Unhandled NONE 64\n");
-+ }
- if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32)
- {
- isym = isymbuf + ELF32_R_SYM (irelscan->r_info);
-diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
-index d47793646b..1cfd441c19 100644
---- a/gas/config/tc-microblaze.c
-+++ b/gas/config/tc-microblaze.c
-@@ -2183,6 +2183,7 @@ md_apply_fix (fixS * fixP,
- else
- fixP->fx_r_type = BFD_RELOC_NONE;
- fixP->fx_addsy = section_symbol (absolute_section);
-+ fixP->fx_done = 0;
- }
- return;
- }
---
-2.15.0
-
diff --git a/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.29/0005-Fixup-MicroBlaze-debug_loc-sections-after-linker-rel.patch b/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.29/0005-Fixup-MicroBlaze-debug_loc-sections-after-linker-rel.patch
deleted file mode 100644
index 9eeb0b2..0000000
--- a/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.29/0005-Fixup-MicroBlaze-debug_loc-sections-after-linker-rel.patch
+++ /dev/null
@@ -1,236 +0,0 @@
-From ef876d5062148e8555353e5e72da87c3a47dea8f Mon Sep 17 00:00:00 2001
-From: Nagaraju Mekala <nagaraju.mekala at xilinx.com>
-Date: Mon, 28 Aug 2017 19:53:56 -0700
-Subject: [PATCH] Fixup MicroBlaze debug_loc sections after linker relaxation
-
-Fixup debug_loc sections after linker relaxation Adds a new reloctype
-R_MICROBLAZE_32_NONE, used for passing reloc info from the assembler to
-the linker when the linker manages to fully resolve a local symbol
-reference.
-
-This is a workaround for design flaws in the assembler to
-linker interface with regards to linker relaxation.
-
-Signed-off-by: Edgar E. Iglesias <edgar.iglesias at gmail.com>
-Signed-off-by: Nagaraju Mekala <nmekala at xilinx.com>
-Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha at xilinx.com>
-Upstream-Status: Pending
----
- bfd/bfd-in2.h | 9 +++++++--
- bfd/elf32-microblaze.c | 42 +++++++++++++++++++++++++++++++++++-------
- bfd/libbfd.h | 1 +
- bfd/reloc.c | 6 ++++++
- binutils/readelf.c | 4 ++++
- gas/config/tc-microblaze.c | 5 ++++-
- include/elf/microblaze.h | 1 +
- 7 files changed, 58 insertions(+), 10 deletions(-)
-
-diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
-index 1343780c8c..3456826f83 100644
---- a/bfd/bfd-in2.h
-+++ b/bfd/bfd-in2.h
-@@ -5809,10 +5809,15 @@ value relative to the read-write small data area anchor */
- expressions of the form "Symbol Op Symbol" */
- BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM,
-
--/* This is a 64 bit reloc that stores the 32 bit pc relative
-+/* This is a 32 bit reloc that stores the 32 bit pc relative
- value in two words (with an imm instruction). No relocation is
- done here - only used for relaxing */
-- BFD_RELOC_MICROBLAZE_64_NONE,
-+ BFD_RELOC_MICROBLAZE_32_NONE,
-+
-+/* This is a 64 bit reloc that stores the 32 bit pc relative
-+ * +value in two words (with an imm instruction). No relocation is
-+ * +done here - only used for relaxing */
-+ BFD_RELOC_MICROBLAZE_64_NONE,
-
- /* This is a 64 bit reloc that stores the 32 bit pc relative
- value in two words (with an imm instruction). The relocation is
-diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c
-index c3dbead48d..1d1f7e210a 100644
---- a/bfd/elf32-microblaze.c
-+++ b/bfd/elf32-microblaze.c
-@@ -176,6 +176,20 @@ static reloc_howto_type microblaze_elf_howto_raw[] =
- 0x0000ffff, /* Dest Mask. */
- FALSE), /* PC relative offset? */
-
-+ HOWTO (R_MICROBLAZE_32_NONE, /* Type. */
-+ 0, /* Rightshift. */
-+ 2, /* Size (0 = byte, 1 = short, 2 = long). */
-+ 32, /* Bitsize. */
-+ TRUE, /* PC_relative. */
-+ 0, /* Bitpos. */
-+ complain_overflow_bitfield, /* Complain on overflow. */
-+ NULL, /* Special Function. */
-+ "R_MICROBLAZE_32_NONE",/* Name. */
-+ FALSE, /* Partial Inplace. */
-+ 0, /* Source Mask. */
-+ 0, /* Dest Mask. */
-+ FALSE), /* PC relative offset? */
-+
- /* This reloc does nothing. Used for relaxation. */
- HOWTO (R_MICROBLAZE_64_NONE, /* Type. */
- 0, /* Rightshift. */
-@@ -532,6 +546,9 @@ microblaze_elf_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED,
- case BFD_RELOC_NONE:
- microblaze_reloc = R_MICROBLAZE_NONE;
- break;
-+ case BFD_RELOC_MICROBLAZE_32_NONE:
-+ microblaze_reloc = R_MICROBLAZE_32_NONE;
-+ break;
- case BFD_RELOC_MICROBLAZE_64_NONE:
- microblaze_reloc = R_MICROBLAZE_64_NONE;
- break;
-@@ -1846,14 +1863,22 @@ microblaze_elf_relax_section (bfd *abfd,
- }
- break;
- case R_MICROBLAZE_NONE:
-+ case R_MICROBLAZE_32_NONE:
- {
- /* This was a PC-relative instruction that was
- completely resolved. */
- int sfix, efix;
-+ unsigned int val;
- bfd_vma target_address;
- target_address = irel->r_addend + irel->r_offset;
- sfix = calc_fixup (irel->r_offset, 0, sec);
- efix = calc_fixup (target_address, 0, sec);
-+
-+ /* Validate the in-band val. */
-+ val = bfd_get_32 (abfd, contents + irel->r_offset);
-+ if (val != irel->r_addend && ELF32_R_TYPE (irel->r_info) == R_MICROBLAZE_32_NONE) {
-+ fprintf(stderr, "%d: CORRUPT relax reloc %x %lx\n", __LINE__, val, irel->r_addend);
-+ }
- irel->r_addend -= (efix - sfix);
- /* Should use HOWTO. */
- microblaze_bfd_write_imm_value_32 (abfd, contents + irel->r_offset,
-@@ -1901,12 +1926,16 @@ microblaze_elf_relax_section (bfd *abfd,
- irelscanend = irelocs + o->reloc_count;
- for (irelscan = irelocs; irelscan < irelscanend; irelscan++)
- {
-- if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_NONE)
-+ if (1 && ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32_NONE)
- {
- unsigned int val;
-
- isym = isymbuf + ELF32_R_SYM (irelscan->r_info);
-
-+ /* hax: We only do the following fixup for debug location lists. */
-+ if (strcmp(".debug_loc", o->name))
-+ continue;
-+
- /* This was a PC-relative instruction that was completely resolved. */
- if (ocontents == NULL)
- {
-@@ -1931,15 +1960,14 @@ microblaze_elf_relax_section (bfd *abfd,
- }
- }
-
-- irelscan->r_addend -= calc_fixup (irelscan->r_addend
-- + isym->st_value, sec);
- val = bfd_get_32 (abfd, ocontents + irelscan->r_offset);
-+ if (val != irelscan->r_addend) {
-+ fprintf(stderr, "%d: CORRUPT relax reloc! %x %lx\n", __LINE__, val, irelscan->r_addend);
-+ }
-+ irelscan->r_addend -= calc_fixup (irelscan->r_addend, 0, sec);
- microblaze_bfd_write_imm_value_32 (abfd, ocontents + irelscan->r_offset,
- irelscan->r_addend);
- }
-- if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_64_NONE) {
-- fprintf(stderr, "Unhandled NONE 64\n");
-- }
- if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32)
- {
- isym = isymbuf + ELF32_R_SYM (irelscan->r_info);
-@@ -1999,7 +2027,7 @@ microblaze_elf_relax_section (bfd *abfd,
- elf_section_data (o)->this_hdr.contents = ocontents;
- }
- }
-- irelscan->r_addend -= calc_fixup (irel->r_addend
-+ irelscan->r_addend -= calc_fixup (irelscan->r_addend
- + isym->st_value,
- 0,
- sec);
-diff --git a/bfd/libbfd.h b/bfd/libbfd.h
-index ae9bf76814..2091286c7c 100644
---- a/bfd/libbfd.h
-+++ b/bfd/libbfd.h
-@@ -2847,6 +2847,7 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",
- "BFD_RELOC_MICROBLAZE_32_ROSDA",
- "BFD_RELOC_MICROBLAZE_32_RWSDA",
- "BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM",
-+ "BFD_RELOC_MICROBLAZE_32_NONE",
- "BFD_RELOC_MICROBLAZE_64_NONE",
- "BFD_RELOC_MICROBLAZE_64_GOTPC",
- "BFD_RELOC_MICROBLAZE_64_GOT",
-diff --git a/bfd/reloc.c b/bfd/reloc.c
-index aa70fa5874..54d7f538ec 100644
---- a/bfd/reloc.c
-+++ b/bfd/reloc.c
-@@ -6860,6 +6860,12 @@ ENUM
- ENUMDOC
- This is a 32 bit reloc for the microblaze to handle
- expressions of the form "Symbol Op Symbol"
-+ENUM
-+ BFD_RELOC_MICROBLAZE_32_NONE
-+ENUMDOC
-+ This is a 32 bit reloc that stores the 32 bit pc relative
-+ value in two words (with an imm instruction). No relocation is
-+ done here - only used for relaxing
- ENUM
- BFD_RELOC_MICROBLAZE_64_NONE
- ENUMDOC
-diff --git a/binutils/readelf.c b/binutils/readelf.c
-index b2f75c0048..8a3226eba9 100644
---- a/binutils/readelf.c
-+++ b/binutils/readelf.c
-@@ -12488,6 +12488,10 @@ is_none_reloc (unsigned int reloc_type)
- || reloc_type == 32 /* R_AVR_DIFF32. */);
- case EM_METAG:
- return reloc_type == 3; /* R_METAG_NONE. */
-+ case EM_MICROBLAZE:
-+ return reloc_type == 30 /* R_MICROBLAZE_32_NONE. */
-+ || reloc_type == 0 /* R_MICROBLAZE_NONE. */
-+ || reloc_type == 9; /* R_MICROBLAZE_64_NONE. */
- case EM_NDS32:
- return (reloc_type == 0 /* R_XTENSA_NONE. */
- || reloc_type == 204 /* R_NDS32_DIFF8. */
-diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
-index 1cfd441c19..e135547e62 100644
---- a/gas/config/tc-microblaze.c
-+++ b/gas/config/tc-microblaze.c
-@@ -2179,7 +2179,9 @@ md_apply_fix (fixS * fixP,
- /* This fixup has been resolved. Create a reloc in case the linker
- moves code around due to relaxing. */
- if (fixP->fx_r_type == BFD_RELOC_64_PCREL)
-- fixP->fx_r_type = BFD_RELOC_MICROBLAZE_64_NONE;
-+ fixP->fx_r_type = BFD_RELOC_MICROBLAZE_64_NONE;
-+ else if (fixP->fx_r_type == BFD_RELOC_32)
-+ fixP->fx_r_type = BFD_RELOC_MICROBLAZE_32_NONE;
- else
- fixP->fx_r_type = BFD_RELOC_NONE;
- fixP->fx_addsy = section_symbol (absolute_section);
-@@ -2401,6 +2403,7 @@ tc_gen_reloc (asection * section ATTRIBUTE_UNUSED, fixS * fixp)
- switch (fixp->fx_r_type)
- {
- case BFD_RELOC_NONE:
-+ case BFD_RELOC_MICROBLAZE_32_NONE:
- case BFD_RELOC_MICROBLAZE_64_NONE:
- case BFD_RELOC_32:
- case BFD_RELOC_MICROBLAZE_32_LO:
-diff --git a/include/elf/microblaze.h b/include/elf/microblaze.h
-index ccb47404c5..abcaea561b 100644
---- a/include/elf/microblaze.h
-+++ b/include/elf/microblaze.h
-@@ -58,6 +58,7 @@ START_RELOC_NUMBERS (elf_microblaze_reloc_type)
- RELOC_NUMBER (R_MICROBLAZE_TLSDTPREL64, 27) /* TLS Offset Within TLS Block */
- RELOC_NUMBER (R_MICROBLAZE_TLSGOTTPREL32, 28) /* TLS Offset From Thread Pointer */
- RELOC_NUMBER (R_MICROBLAZE_TLSTPREL32, 29) /* TLS Offset From Thread Pointer */
-+ RELOC_NUMBER (R_MICROBLAZE_32_NONE, 30)
-
- END_RELOC_NUMBERS (R_MICROBLAZE_max)
-
---
-2.15.0
-
diff --git a/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.29/0006-Fix-bug-in-MicroBlaze-TLSTPREL-Relocation.patch b/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.29/0006-Fix-bug-in-MicroBlaze-TLSTPREL-Relocation.patch
deleted file mode 100644
index de458ad..0000000
--- a/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.29/0006-Fix-bug-in-MicroBlaze-TLSTPREL-Relocation.patch
+++ /dev/null
@@ -1,37 +0,0 @@
-From b55dddad1303aafe249e2ba0ddf20460f8f035f6 Mon Sep 17 00:00:00 2001
-From: Nagaraju Mekala <nagaraju.mekala at xilinx.com>
-Date: Mon, 28 Aug 2017 19:53:58 -0700
-Subject: [PATCH] Fix bug in MicroBlaze TLSTPREL Relocation
-
-Fixed the problem related to the fixup/relocations TLSTPREL.
-When the fixup is applied the addend is not added at the correct offset
-of the instruction. The offset is hard coded considering its big endian
-and it fails for Little endian. This patch allows support for both
-big & little-endian compilers
-
-Signed-off-by: Nagaraju Mekala <nagaraju.mekala at xilinx.com>
-Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha at xilinx.com>
-Upstream-Status: Pending
----
- bfd/elf32-microblaze.c | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
-diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c
-index 1d1f7e210a..cc6e4b1fd9 100644
---- a/bfd/elf32-microblaze.c
-+++ b/bfd/elf32-microblaze.c
-@@ -1417,9 +1417,9 @@ microblaze_elf_relocate_section (bfd *output_bfd,
- relocation += addend;
- relocation -= dtprel_base(info);
- bfd_put_16 (input_bfd, (relocation >> 16) & 0xffff,
-- contents + offset + 2);
-+ contents + offset + endian);
- bfd_put_16 (input_bfd, relocation & 0xffff,
-- contents + offset + 2 + INST_WORD_SIZE);
-+ contents + offset + endian + INST_WORD_SIZE);
- break;
- case (int) R_MICROBLAZE_64_PCREL :
- case (int) R_MICROBLAZE_64:
---
-2.15.0
-
diff --git a/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.29/0007-Add-MicroBlaze-address-extension-instructions.patch b/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.29/0007-Add-MicroBlaze-address-extension-instructions.patch
deleted file mode 100644
index ad62345..0000000
--- a/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.29/0007-Add-MicroBlaze-address-extension-instructions.patch
+++ /dev/null
@@ -1,106 +0,0 @@
-From 82c8eacbceb51422d3da75ac30912f9dedc0e832 Mon Sep 17 00:00:00 2001
-From: Nagaraju Mekala <nagaraju.mekala at xilinx.com>
-Date: Mon, 28 Aug 2017 19:53:59 -0700
-Subject: [PATCH] Add MicroBlaze address extension instructions
-
-This patch adds the support of new instructions which are required
-for supporting Address extension feature.
-
-2016-01-18 Nagaraju Mekala <nagaraju.mekala at xilinx.com>
-
- * microblaze-opc.h (op_code_struct): Added new instructions
- * microblaze-opcm.h (microblaze_instr): Added new instructions
-
-Signed-off-by: Nagaraju Mekala <nagaraju.mekala at xilinx.com>
-Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha at xilinx.com>
-Upstream-Status: Pending
----
- opcodes/microblaze-opc.h | 13 ++++++++++++-
- opcodes/microblaze-opcm.h | 10 +++++-----
- 2 files changed, 17 insertions(+), 6 deletions(-)
-
-diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
-index b33178145f..a64f8362da 100644
---- a/opcodes/microblaze-opc.h
-+++ b/opcodes/microblaze-opc.h
-@@ -102,7 +102,7 @@
- #define DELAY_SLOT 1
- #define NO_DELAY_SLOT 0
-
--#define MAX_OPCODES 291
-+#define MAX_OPCODES 299
-
- struct op_code_struct
- {
-@@ -178,8 +178,11 @@ struct op_code_struct
- {"wdc.ext.clear", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000466, OPCODE_MASK_H35B, wdcextclear, special_inst },
- {"wdc.flush", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000074, OPCODE_MASK_H34B, wdcflush, special_inst },
- {"wdc.ext.flush", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000476, OPCODE_MASK_H35B, wdcextflush, special_inst },
-+ {"wdc.clear.ea", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900000E6, OPCODE_MASK_H34B, wdcclearea, special_inst },
- {"mts", INST_TYPE_SPECIAL_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MTS, 0x9400C000, OPCODE_MASK_H13S, mts, special_inst },
-+ {"mtse", INST_TYPE_SPECIAL_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MTS, 0x9500C000, OPCODE_MASK_H13S, mtse,special_inst },
- {"mfs", INST_TYPE_RD_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MFS, 0x94008000, OPCODE_MASK_H23S, mfs, special_inst },
-+ {"mfse", INST_TYPE_RD_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MFS, 0x94088000, OPCODE_MASK_H23S, mfse, special_inst },
- {"br", INST_TYPE_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98000000, OPCODE_MASK_H124, br, branch_inst },
- {"brd", INST_TYPE_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98100000, OPCODE_MASK_H124, brd, branch_inst },
- {"brld", INST_TYPE_RD_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98140000, OPCODE_MASK_H24, brld, branch_inst },
-@@ -229,18 +232,24 @@ struct op_code_struct
- {"bgeid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBEA00000, OPCODE_MASK_H1, bgeid, branch_inst },
- {"lbu", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC0000000, OPCODE_MASK_H4, lbu, memory_load_inst },
- {"lbur", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC0000200, OPCODE_MASK_H4, lbur, memory_load_inst },
-+ {"lbuea", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC0000080, OPCODE_MASK_H4, lbuea, memory_load_inst },
- {"lhu", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC4000000, OPCODE_MASK_H4, lhu, memory_load_inst },
- {"lhur", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC4000200, OPCODE_MASK_H4, lhur, memory_load_inst },
-+ {"lhuea", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC4000080, OPCODE_MASK_H4, lhuea, memory_load_inst },
- {"lw", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000000, OPCODE_MASK_H4, lw, memory_load_inst },
- {"lwr", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000200, OPCODE_MASK_H4, lwr, memory_load_inst },
- {"lwx", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000400, OPCODE_MASK_H4, lwx, memory_load_inst },
-+ {"lwea", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000080, OPCODE_MASK_H4, lwea, memory_load_inst },
- {"sb", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD0000000, OPCODE_MASK_H4, sb, memory_store_inst },
- {"sbr", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD0000200, OPCODE_MASK_H4, sbr, memory_store_inst },
-+ {"sbea", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD0000080, OPCODE_MASK_H4, sbea, memory_store_inst },
- {"sh", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD4000000, OPCODE_MASK_H4, sh, memory_store_inst },
- {"shr", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD4000200, OPCODE_MASK_H4, shr, memory_store_inst },
-+ {"shea", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD4000080, OPCODE_MASK_H4, shea, memory_store_inst },
- {"sw", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000000, OPCODE_MASK_H4, sw, memory_store_inst },
- {"swr", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000200, OPCODE_MASK_H4, swr, memory_store_inst },
- {"swx", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000400, OPCODE_MASK_H4, swx, memory_store_inst },
-+ {"swea", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000080, OPCODE_MASK_H4, swea, memory_store_inst },
- {"lbui", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE0000000, OPCODE_MASK_H, lbui, memory_load_inst },
- {"lhui", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE4000000, OPCODE_MASK_H, lhui, memory_load_inst },
- {"lwi", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE8000000, OPCODE_MASK_H, lwi, memory_load_inst },
-@@ -405,6 +414,8 @@ struct op_code_struct
- {"clz", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900000E0, OPCODE_MASK_H34, clz, special_inst },
- {"mbar", INST_TYPE_IMM5, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8020004, OPCODE_MASK_HN, mbar, special_inst },
- {"sleep", INST_TYPE_NONE, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBA020004, OPCODE_MASK_HN, invalid_inst, special_inst }, /* translates to mbar 16. */
-+ {"hibernate", INST_TYPE_NONE, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB9020004, OPCODE_MASK_HN, invalid_inst, special_inst }, /* translates to mbar 8. */
-+ {"suspend", INST_TYPE_NONE, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBB020004, OPCODE_MASK_HN, invalid_inst, special_inst }, /* translates to mbar 24. */
- {"swapb", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900001E0, OPCODE_MASK_H4, swapb, arithmetic_inst },
- {"swaph", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900001E2, OPCODE_MASK_H4, swaph, arithmetic_inst },
- {"", 0, 0, 0, 0, 0, 0, 0, 0},
-diff --git a/opcodes/microblaze-opcm.h b/opcodes/microblaze-opcm.h
-index 00dc131302..21a3dc8d76 100644
---- a/opcodes/microblaze-opcm.h
-+++ b/opcodes/microblaze-opcm.h
-@@ -33,13 +33,13 @@ enum microblaze_instr
- /* 'or/and/xor' are C++ keywords. */
- microblaze_or, microblaze_and, microblaze_xor,
- andn, pcmpbf, pcmpbc, pcmpeq, pcmpne, sra, src, srl, sext8, sext16,
-- wic, wdc, wdcclear, wdcextclear, wdcflush, wdcextflush, mts, mfs, mbar, br,
-- brd, brld, bra, brad, brald, microblaze_brk, beq, beqd, bne, bned, blt,
-- bltd, ble, bled, bgt, bgtd, bge, bged, ori, andi, xori, andni,
-+ wic, wdc, wdcclear, wdcextclear, wdcflush, wdcextflush, wdcclearea, mts, mtse,
-+ mfs, mfse, mbar, br, brd, brld, bra, brad, brald, microblaze_brk, beq, beqd,
-+ bne, bned, blt, bltd, ble, bled, bgt, bgtd, bge, bged, ori, andi, xori, andni,
- imm, rtsd, rtid, rtbd, rted, bri, brid, brlid, brai, braid, bralid,
- brki, beqi, beqid, bnei, bneid, blti, bltid, blei, bleid, bgti,
-- bgtid, bgei, bgeid, lbu, lbur, lhu, lhur, lw, lwr, lwx, sb, sbr, sh,
-- shr, sw, swr, swx, lbui, lhui, lwi,
-+ bgtid, bgei, bgeid, lbu, lbuea, lbur, lhu, lhuea, lhur, lw, lwea, lwr, lwx,
-+ sb, sbea, sbr, sh, shea, shr, sw, swea, swr, swx, lbui, lhui, lwi,
- sbi, shi, swi, msrset, msrclr, tuqula, fadd, frsub, fmul, fdiv,
- fcmp_lt, fcmp_eq, fcmp_le, fcmp_gt, fcmp_ne, fcmp_ge, fcmp_un, flt,
- fint, fsqrt,
---
-2.15.0
-
diff --git a/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.29/0008-Add-new-MicroBlaze-bit-field-instructions.patch b/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.29/0008-Add-new-MicroBlaze-bit-field-instructions.patch
deleted file mode 100644
index 0bc0117..0000000
--- a/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.29/0008-Add-new-MicroBlaze-bit-field-instructions.patch
+++ /dev/null
@@ -1,232 +0,0 @@
-From 5c4dacaae2ba93569c1d37cda9859c57d6649dc0 Mon Sep 17 00:00:00 2001
-From: Nagaraju Mekala <nagaraju.mekala at xilinx.com>
-Date: Mon, 28 Aug 2017 19:54:01 -0700
-Subject: [PATCH] Add new MicroBlaze bit-field instructions
-
-This patches adds new bsefi and bsifi instructions. BSEFI- The
-instruction shall extract a bit field from a register and place it
-right-adjusted in the destination register. The other bits in the
-destination register shall be set to zero BSIFI- The instruction shall
-insert a right-adjusted bit field from a register at another position in
-the destination register. The rest of the bits in the destination
-register shall be unchanged
-
-Signed-off-by: Nagaraju Mekala <nagaraju.mekala at xilinx.com>
-Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha at xilinx.com>
-Upstream-Status: Pending
----
- gas/config/tc-microblaze.c | 71 +++++++++++++++++++++++++++++++++++++++++++++-
- opcodes/microblaze-dis.c | 16 +++++++++++
- opcodes/microblaze-opc.h | 12 +++++++-
- opcodes/microblaze-opcm.h | 6 +++-
- 4 files changed, 102 insertions(+), 3 deletions(-)
-
-diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
-index e135547e62..34cb80fac2 100644
---- a/gas/config/tc-microblaze.c
-+++ b/gas/config/tc-microblaze.c
-@@ -909,7 +909,7 @@ md_assemble (char * str)
- unsigned reg2;
- unsigned reg3;
- unsigned isize;
-- unsigned int immed, temp;
-+ unsigned int immed, immed2, temp;
- expressionS exp;
- char name[20];
-
-@@ -1164,7 +1164,76 @@ md_assemble (char * str)
- inst |= (reg2 << RA_LOW) & RA_MASK;
- inst |= (immed << IMM_LOW) & IMM5_MASK;
- break;
-+ case INST_TYPE_RD_R1_IMM5_IMM5:
-+ if (strcmp (op_end, ""))
-+ op_end = parse_reg (op_end + 1, ®1); /* Get rd. */
-+ else
-+ {
-+ as_fatal (_("Error in statement syntax"));
-+ reg1 = 0;
-+ }
-+ if (strcmp (op_end, ""))
-+ op_end = parse_reg (op_end + 1, ®2); /* Get r1. */
-+ else
-+ {
-+ as_fatal (_("Error in statement syntax"));
-+ reg2 = 0;
-+ }
-+
-+ /* Check for spl registers. */
-+ if (check_spl_reg (®1))
-+ as_fatal (_("Cannot use special register with this instruction"));
-+ if (check_spl_reg (®2))
-+ as_fatal (_("Cannot use special register with this instruction"));
-
-+ /* Width immediate value. */
-+ if (strcmp (op_end, ""))
-+ op_end = parse_imm (op_end + 1, &exp, MIN_IMM_WIDTH, MAX_IMM_WIDTH);
-+ else
-+ as_fatal (_("Error in statement syntax"));
-+ if (exp.X_op != O_constant)
-+ {
-+ as_warn (_("Symbol used as immediate width value for bit field instruction"));
-+ immed = 1;
-+ }
-+ else
-+ immed = exp.X_add_number;
-+ if (opcode->instr == bsefi && immed > 31)
-+ as_fatal (_("Width value must be less than 32"));
-+
-+ /* Shift immediate value. */
-+ if (strcmp (op_end, ""))
-+ op_end = parse_imm (op_end + 1, &exp, MIN_IMM, MAX_IMM);
-+ else
-+ as_fatal (_("Error in statement syntax"));
-+ if (exp.X_op != O_constant)
-+ {
-+ as_warn (_("Symbol used as immediate shift value for bit field instruction"));
-+ immed2 = 0;
-+ }
-+ else
-+ {
-+ output = frag_more (isize);
-+ immed2 = exp.X_add_number;
-+ }
-+ if (immed2 != (immed2 % 32))
-+ {
-+ as_warn (_("Shift value greater than 32. using <value %% 32>"));
-+ immed2 = immed2 % 32;
-+ }
-+
-+ /* Check combined value. */
-+ if (immed + immed2 > 32)
-+ as_fatal (_("Width value + shift value must not be greater than 32"));
-+
-+ inst |= (reg1 << RD_LOW) & RD_MASK;
-+ inst |= (reg2 << RA_LOW) & RA_MASK;
-+ if (opcode->instr == bsefi)
-+ inst |= (immed & IMM5_MASK) << IMM_WIDTH_LOW; /* bsefi */
-+ else
-+ inst |= ((immed + immed2 - 1) & IMM5_MASK) << IMM_WIDTH_LOW; /* bsifi */
-+ inst |= (immed2 << IMM_LOW) & IMM5_MASK;
-+ break;
- case INST_TYPE_R1_R2:
- if (strcmp (op_end, ""))
- op_end = parse_reg (op_end + 1, ®1); /* Get r1. */
-diff --git a/opcodes/microblaze-dis.c b/opcodes/microblaze-dis.c
-index 6a174b0eb9..80a47ad2fc 100644
---- a/opcodes/microblaze-dis.c
-+++ b/opcodes/microblaze-dis.c
-@@ -73,6 +73,18 @@ get_field_imm5_mbar (long instr)
- return(strdup(tmpstr));
- }
-
-+static char *
-+get_field_imm5width (long instr)
-+{
-+ char tmpstr[25];
-+
-+ if (instr & 0x00004000)
-+ sprintf (tmpstr, "%d", (short)(((instr & IMM5_WIDTH_MASK) >> IMM_WIDTH_LOW))); /* bsefi */
-+ else
-+ sprintf (tmpstr, "%d", (short)(((instr & IMM5_WIDTH_MASK) >> IMM_WIDTH_LOW) - ((instr & IMM5_MASK) >> IMM_LOW) + 1)); /* bsifi */
-+ return (strdup (tmpstr));
-+}
-+
- static char *
- get_field_rfsl (long instr)
- {
-@@ -396,6 +408,10 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info)
- /* For mbar 16 or sleep insn. */
- case INST_TYPE_NONE:
- break;
-+ /* For bit field insns. */
-+ case INST_TYPE_RD_R1_IMM5_IMM5:
-+ print_func (stream, "\t%s, %s, %s, %s", get_field_rd (inst),get_field_r1(inst),get_field_imm5width (inst), get_field_imm5 (inst));
-+ break;
- /* For tuqula instruction */
- case INST_TYPE_RD:
- print_func (stream, "\t%s", get_field_rd (inst));
-diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
-index a64f8362da..afb34989d9 100644
---- a/opcodes/microblaze-opc.h
-+++ b/opcodes/microblaze-opc.h
-@@ -59,6 +59,9 @@
- /* For mbar. */
- #define INST_TYPE_IMM5 20
-
-+/* For bsefi and bsifi */
-+#define INST_TYPE_RD_R1_IMM5_IMM5 21
-+
- #define INST_TYPE_NONE 25
-
-
-@@ -89,7 +92,9 @@
- #define OPCODE_MASK_H124 0xFFFF07FF /* High 16, and low 11 bits. */
- #define OPCODE_MASK_H1234 0xFFFFFFFF /* All 32 bits. */
- #define OPCODE_MASK_H3 0xFC000600 /* High 6 bits and bits 21, 22. */
-+#define OPCODE_MASK_H3B 0xFC00C600 /* High 6 bits and bits 16, 17, 21, 22. */
- #define OPCODE_MASK_H32 0xFC00FC00 /* High 6 bits and bit 16-21. */
-+#define OPCODE_MASK_H32B 0xFC00C000 /* High 6 bits and bit 16, 17. */
- #define OPCODE_MASK_H34B 0xFC0000FF /* High 6 bits and low 8 bits. */
- #define OPCODE_MASK_H35B 0xFC0004FF /* High 6 bits and low 9 bits. */
- #define OPCODE_MASK_H34C 0xFC0007E0 /* High 6 bits and bits 21-26. */
-@@ -102,7 +107,7 @@
- #define DELAY_SLOT 1
- #define NO_DELAY_SLOT 0
-
--#define MAX_OPCODES 299
-+#define MAX_OPCODES 301
-
- struct op_code_struct
- {
-@@ -159,6 +164,8 @@ struct op_code_struct
- {"bslli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000400, OPCODE_MASK_H3, bslli, barrel_shift_inst },
- {"bsrai", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000200, OPCODE_MASK_H3, bsrai, barrel_shift_inst },
- {"bsrli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000000, OPCODE_MASK_H3, bsrli, barrel_shift_inst },
-+ {"bsefi", INST_TYPE_RD_R1_IMM5_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64004000, OPCODE_MASK_H32B, bsefi, barrel_shift_inst },
-+ {"bsifi", INST_TYPE_RD_R1_IMM5_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64008000, OPCODE_MASK_H32B, bsifi, barrel_shift_inst },
- {"or", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x80000000, OPCODE_MASK_H4, microblaze_or, logical_inst },
- {"and", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x84000000, OPCODE_MASK_H4, microblaze_and, logical_inst },
- {"xor", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x88000000, OPCODE_MASK_H4, microblaze_xor, logical_inst },
-@@ -438,5 +445,8 @@ char pvr_register_prefix[] = "rpvr";
- #define MIN_IMM5 ((int) 0x00000000)
- #define MAX_IMM5 ((int) 0x0000001f)
-
-+#define MIN_IMM_WIDTH ((int) 0x00000001)
-+#define MAX_IMM_WIDTH ((int) 0x00000020)
-+
- #endif /* MICROBLAZE_OPC */
-
-diff --git a/opcodes/microblaze-opcm.h b/opcodes/microblaze-opcm.h
-index 21a3dc8d76..dd6be7f65c 100644
---- a/opcodes/microblaze-opcm.h
-+++ b/opcodes/microblaze-opcm.h
-@@ -29,7 +29,7 @@ enum microblaze_instr
- addi, rsubi, addic, rsubic, addik, rsubik, addikc, rsubikc, mul,
- mulh, mulhu, mulhsu,swapb,swaph,
- idiv, idivu, bsll, bsra, bsrl, get, put, nget, nput, cget, cput,
-- ncget, ncput, muli, bslli, bsrai, bsrli, mului,
-+ ncget, ncput, muli, bslli, bsrai, bsrli, bsefi, bsifi, mului,
- /* 'or/and/xor' are C++ keywords. */
- microblaze_or, microblaze_and, microblaze_xor,
- andn, pcmpbf, pcmpbc, pcmpeq, pcmpne, sra, src, srl, sext8, sext16,
-@@ -129,6 +129,7 @@ enum microblaze_instr_type
- #define RB_LOW 11 /* Low bit for RB. */
- #define IMM_LOW 0 /* Low bit for immediate. */
- #define IMM_MBAR 21 /* low bit for mbar instruction. */
-+#define IMM_WIDTH_LOW 6 /* Low bit for immediate width */
-
- #define RD_MASK 0x03E00000
- #define RA_MASK 0x001F0000
-@@ -141,6 +142,9 @@ enum microblaze_instr_type
- /* Imm mask for mbar. */
- #define IMM5_MBAR_MASK 0x03E00000
-
-+/* Imm mask for extract/insert width. */
-+#define IMM5_WIDTH_MASK 0x000007C0
-+
- /* FSL imm mask for get, put instructions. */
- #define RFSL_MASK 0x000000F
-
---
-2.15.0
-
diff --git a/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.29/0009-Fixing-MicroBlaze-IMM-bug.patch b/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.29/0009-Fixing-MicroBlaze-IMM-bug.patch
deleted file mode 100644
index 0eef0f0..0000000
--- a/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.29/0009-Fixing-MicroBlaze-IMM-bug.patch
+++ /dev/null
@@ -1,31 +0,0 @@
-From cff770a6f73b82db3259e9577e13b08a1bcd14e8 Mon Sep 17 00:00:00 2001
-From: Nagaraju Mekala <nagaraju.mekala at xilinx.com>
-Date: Mon, 28 Aug 2017 19:54:02 -0700
-Subject: [PATCH] Fixing MicroBlaze IMM bug
-
-Fixing the imm bug. with relax option imm -1 is also getting removed this is corrected now.
-
-Signed-off-by: Nagaraju Mekala <nagaraju.mekala at xilinx.com>
-Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha at xilinx.com>
-Upstream-Status: Pending
----
- bfd/elf32-microblaze.c | 3 +--
- 1 file changed, 1 insertion(+), 2 deletions(-)
-
-diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c
-index cc6e4b1fd9..6fc475cbcd 100644
---- a/bfd/elf32-microblaze.c
-+++ b/bfd/elf32-microblaze.c
-@@ -1803,8 +1803,7 @@ microblaze_elf_relax_section (bfd *abfd,
- else
- symval += irel->r_addend;
-
-- if ((symval & 0xffff8000) == 0
-- || (symval & 0xffff8000) == 0xffff8000)
-+ if ((symval & 0xffff8000) == 0)
- {
- /* We can delete this instruction. */
- sec->relax[sec->relax_count].addr = irel->r_offset;
---
-2.15.0
-
diff --git a/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.29/0010-Fixed-bug-in-GCC-so-that-it-will-support-.long-0U-an.patch b/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.29/0010-Fixed-bug-in-GCC-so-that-it-will-support-.long-0U-an.patch
deleted file mode 100644
index e08bedc..0000000
--- a/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.29/0010-Fixed-bug-in-GCC-so-that-it-will-support-.long-0U-an.patch
+++ /dev/null
@@ -1,36 +0,0 @@
-From 4449e15997a576761433cc76daf3635742acec62 Mon Sep 17 00:00:00 2001
-From: Mahesh Bodapati <mbodapat at xilinx.com>
-Date: Wed, 15 Nov 2017 17:45:35 -0800
-Subject: [PATCH] Fixed bug in GCC so that it will support .long 0U and .long
- 0u
-
-Signed-off-by: Mahesh Bodapati <mbodapat at xilinx.com>
-Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha at xilinx.com>
-Upstream-Status: Pending
----
- gas/expr.c | 9 +++++++++
- 1 file changed, 9 insertions(+)
-
-diff --git a/gas/expr.c b/gas/expr.c
-index 6fc707b8a5..a54b1f4b76 100644
---- a/gas/expr.c
-+++ b/gas/expr.c
-@@ -810,6 +810,15 @@ operand (expressionS *expressionP, enum expr_mode mode)
- break;
- }
- }
-+ if ((*input_line_pointer == 'U') || (*input_line_pointer == 'u'))
-+ {
-+ input_line_pointer--;
-+
-+ integer_constant ((NUMBERS_WITH_SUFFIX || flag_m68k_mri)
-+ ? 0 : 10,
-+ expressionP);
-+ break;
-+ }
- c = *input_line_pointer;
- switch (c)
- {
---
-2.15.0
-
diff --git a/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.29/0011-Fixing-MicroBlaze-constant-range-check-issue.patch b/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.29/0011-Fixing-MicroBlaze-constant-range-check-issue.patch
deleted file mode 100644
index fe94090..0000000
--- a/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.29/0011-Fixing-MicroBlaze-constant-range-check-issue.patch
+++ /dev/null
@@ -1,30 +0,0 @@
-From 4286d83d6dc58131982247f7017b738595329771 Mon Sep 17 00:00:00 2001
-From: Nagaraju Mekala <nagaraju.mekala at xilinx.com>
-Date: Wed, 15 Nov 2017 17:45:34 -0800
-Subject: [PATCH] Fixing MicroBlaze constant range check issue
-
-Sample error: not in range ffffffff80000000..7fffffff, not ffffffff70000000
-
-Signed-off-by: Nagaraju Mekala <nagaraju.mekala at xilinx.com>
-Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha at xilinx.com>
-Upstream-Status: Pending
----
- gas/config/tc-microblaze.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
-index 34cb80fac2..7e1233945a 100644
---- a/gas/config/tc-microblaze.c
-+++ b/gas/config/tc-microblaze.c
-@@ -749,7 +749,7 @@ parse_imm (char * s, expressionS * e, offsetT min, offsetT max)
- if ((e->X_add_number >> 31) == 1)
- e->X_add_number |= -((addressT) (1U << 31));
-
-- if (e->X_add_number < min || e->X_add_number > max)
-+ if ((int)e->X_add_number < min || (int)e->X_add_number > max)
- {
- as_fatal (_("operand must be absolute in range %lx..%lx, not %lx"),
- (long) min, (long) max, (long) e->X_add_number);
---
-2.15.0
-
diff --git a/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.29/0012-MicroBlaze-fix-mask-for-barrel-shift-instructions.patch b/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.29/0012-MicroBlaze-fix-mask-for-barrel-shift-instructions.patch
deleted file mode 100644
index 1028c50..0000000
--- a/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.29/0012-MicroBlaze-fix-mask-for-barrel-shift-instructions.patch
+++ /dev/null
@@ -1,38 +0,0 @@
-From a3ce2a329f583a66732b6a435c1bd76a83732dd8 Mon Sep 17 00:00:00 2001
-From: Nathan Rossi <nathan at nathanrossi.com>
-Date: Sun, 5 Nov 2017 22:17:39 +1000
-Subject: [PATCH] MicroBlaze fix mask for barrel shift instructions
-
-As of v10.0 the bsi (bslli/bsrai/bsrli/bsefi/bsifi) instructions have
-bits 16 and 17 defined as 'Insert' and 'Extract' respectively to support
-bit field insert/extract operations. For the bslli/bsrai/bsrli
-instructions these bits must be 0, as such update the opcode mask so
-that the bslli/bsrai/bsrli instructions do not also match the bsefi and
-bsifi instructions.
-
-Signed-off-by: Nathan Rossi <nathan at nathanrossi.com>
-Upstream-Status: Pending
----
- opcodes/microblaze-opc.h | 6 +++---
- 1 file changed, 3 insertions(+), 3 deletions(-)
-
-diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
-index afb34989d9..68db818d69 100644
---- a/opcodes/microblaze-opc.h
-+++ b/opcodes/microblaze-opc.h
-@@ -161,9 +161,9 @@ struct op_code_struct
- {"ncget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C006000, OPCODE_MASK_H32, ncget, anyware_inst },
- {"ncput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00E000, OPCODE_MASK_H32, ncput, anyware_inst },
- {"muli", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x60000000, OPCODE_MASK_H, muli, mult_inst },
-- {"bslli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000400, OPCODE_MASK_H3, bslli, barrel_shift_inst },
-- {"bsrai", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000200, OPCODE_MASK_H3, bsrai, barrel_shift_inst },
-- {"bsrli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000000, OPCODE_MASK_H3, bsrli, barrel_shift_inst },
-+ {"bslli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000400, OPCODE_MASK_H3B, bslli, barrel_shift_inst },
-+ {"bsrai", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000200, OPCODE_MASK_H3B, bsrai, barrel_shift_inst },
-+ {"bsrli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000000, OPCODE_MASK_H3B, bsrli, barrel_shift_inst },
- {"bsefi", INST_TYPE_RD_R1_IMM5_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64004000, OPCODE_MASK_H32B, bsefi, barrel_shift_inst },
- {"bsifi", INST_TYPE_RD_R1_IMM5_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64008000, OPCODE_MASK_H32B, bsifi, barrel_shift_inst },
- {"or", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x80000000, OPCODE_MASK_H4, microblaze_or, logical_inst },
---
-2.15.0
-
diff --git a/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0001-MicroBlaze-Add-wdc.ext.clear-and-wdc.ext.flush-insns.patch b/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0001-MicroBlaze-Add-wdc.ext.clear-and-wdc.ext.flush-insns.patch
new file mode 100644
index 0000000..878bb32
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0001-MicroBlaze-Add-wdc.ext.clear-and-wdc.ext.flush-insns.patch
@@ -0,0 +1,65 @@
+From 91f39b692c48336117c092e4afd80899c97779e6 Mon Sep 17 00:00:00 2001
+From: David Holsgrove <david.holsgrove at xilinx.com>
+Date: Mon, 28 Aug 2017 19:53:52 -0700
+Subject: [PATCH] MicroBlaze Add wdc.ext.clear and wdc.ext.flush insns
+
+Added two new instructions, wdc.ext.clear and wdc.ext.flush,
+to enable MicroBlaze to flush an external cache, which is
+used with the new coherency support for multiprocessing.
+
+Signed-off-by: David Holsgrove <david.holsgrove at xilinx.com>
+Signed-off-by: Nagaraju Mekala <nagaraju.mekala at xilinx.com>
+Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha at xilinx.com>
+Upstream-Status: Pending
+
+---
+ opcodes/microblaze-opc.h | 5 ++++-
+ opcodes/microblaze-opcm.h | 4 ++--
+ 2 files changed, 6 insertions(+), 3 deletions(-)
+
+diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
+index ede8af8..773dc81 100644
+--- a/opcodes/microblaze-opc.h
++++ b/opcodes/microblaze-opc.h
+@@ -91,6 +91,7 @@
+ #define OPCODE_MASK_H3 0xFC000600 /* High 6 bits and bits 21, 22. */
+ #define OPCODE_MASK_H32 0xFC00FC00 /* High 6 bits and bit 16-21. */
+ #define OPCODE_MASK_H34B 0xFC0000FF /* High 6 bits and low 8 bits. */
++#define OPCODE_MASK_H35B 0xFC0004FF /* High 6 bits and low 9 bits. */
+ #define OPCODE_MASK_H34C 0xFC0007E0 /* High 6 bits and bits 21-26. */
+
+ /* New Mask for msrset, msrclr insns. */
+@@ -101,7 +102,7 @@
+ #define DELAY_SLOT 1
+ #define NO_DELAY_SLOT 0
+
+-#define MAX_OPCODES 289
++#define MAX_OPCODES 291
+
+ struct op_code_struct
+ {
+@@ -174,7 +175,9 @@ struct op_code_struct
+ {"wic", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000068, OPCODE_MASK_H34B, wic, special_inst },
+ {"wdc", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000064, OPCODE_MASK_H34B, wdc, special_inst },
+ {"wdc.clear", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000066, OPCODE_MASK_H34B, wdcclear, special_inst },
++ {"wdc.ext.clear", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000466, OPCODE_MASK_H35B, wdcextclear, special_inst },
+ {"wdc.flush", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000074, OPCODE_MASK_H34B, wdcflush, special_inst },
++ {"wdc.ext.flush", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000476, OPCODE_MASK_H35B, wdcextflush, special_inst },
+ {"mts", INST_TYPE_SPECIAL_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MTS, 0x9400C000, OPCODE_MASK_H13S, mts, special_inst },
+ {"mfs", INST_TYPE_RD_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MFS, 0x94008000, OPCODE_MASK_H23S, mfs, special_inst },
+ {"br", INST_TYPE_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98000000, OPCODE_MASK_H124, br, branch_inst },
+diff --git a/opcodes/microblaze-opcm.h b/opcodes/microblaze-opcm.h
+index 92f3f19..7338f6a 100644
+--- a/opcodes/microblaze-opcm.h
++++ b/opcodes/microblaze-opcm.h
+@@ -33,8 +33,8 @@ enum microblaze_instr
+ /* 'or/and/xor' are C++ keywords. */
+ microblaze_or, microblaze_and, microblaze_xor,
+ andn, pcmpbf, pcmpbc, pcmpeq, pcmpne, sra, src, srl, sext8, sext16,
+- wic, wdc, wdcclear, wdcflush, mts, mfs, mbar, br, brd,
+- brld, bra, brad, brald, microblaze_brk, beq, beqd, bne, bned, blt,
++ wic, wdc, wdcclear, wdcextclear, wdcflush, wdcextflush, mts, mfs, mbar, br,
++ brd, brld, bra, brad, brald, microblaze_brk, beq, beqd, bne, bned, blt,
+ bltd, ble, bled, bgt, bgtd, bge, bged, ori, andi, xori, andni,
+ imm, rtsd, rtid, rtbd, rted, bri, brid, brlid, brai, braid, bralid,
+ brki, beqi, beqid, bnei, bneid, blti, bltid, blei, bleid, bgti,
diff --git a/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0002-MicroBlaze-add-mlittle-endian-and-mbig-endian-flags.patch b/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0002-MicroBlaze-add-mlittle-endian-and-mbig-endian-flags.patch
new file mode 100644
index 0000000..edeecfd
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0002-MicroBlaze-add-mlittle-endian-and-mbig-endian-flags.patch
@@ -0,0 +1,64 @@
+From 8b733a61ab54ba4cedb234020562502d20eebcbb Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nagaraju.mekala at xilinx.com>
+Date: Mon, 28 Aug 2017 19:53:53 -0700
+Subject: [PATCH] MicroBlaze add mlittle-endian and mbig-endian flags
+
+Added support in gas for mlittle-endian and mbig-endian flags
+as options.
+
+Updated show usage for MicroBlaze specific assembler options
+to include new entries.
+
+Signed-off-by: Nagaraju Mekala <nagaraju.mekala at xilinx.com>
+Signed-off-by: David Holsgrove <david.holsgrove at xilinx.com>
+Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha at xilinx.com>
+Upstream-Status: Pending
+
+---
+ gas/config/tc-microblaze.c | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
+index 0194cd9..42dd7ae 100644
+--- a/gas/config/tc-microblaze.c
++++ b/gas/config/tc-microblaze.c
+@@ -37,6 +37,8 @@
+
+ #define OPTION_EB (OPTION_MD_BASE + 0)
+ #define OPTION_EL (OPTION_MD_BASE + 1)
++#define OPTION_LITTLE (OPTION_MD_BASE + 2)
++#define OPTION_BIG (OPTION_MD_BASE + 3)
+
+ void microblaze_generate_symbol (char *sym);
+ static bfd_boolean check_spl_reg (unsigned *);
+@@ -1837,6 +1839,8 @@ struct option md_longopts[] =
+ {
+ {"EB", no_argument, NULL, OPTION_EB},
+ {"EL", no_argument, NULL, OPTION_EL},
++ {"mlittle-endian", no_argument, NULL, OPTION_LITTLE},
++ {"mbig-endian", no_argument, NULL, OPTION_BIG},
+ { NULL, no_argument, NULL, 0}
+ };
+
+@@ -2471,9 +2475,11 @@ md_parse_option (int c, const char * arg ATTRIBUTE_UNUSED)
+ switch (c)
+ {
+ case OPTION_EB:
++ case OPTION_BIG:
+ target_big_endian = 1;
+ break;
+ case OPTION_EL:
++ case OPTION_LITTLE:
+ target_big_endian = 0;
+ break;
+ default:
+@@ -2488,6 +2494,9 @@ md_show_usage (FILE * stream ATTRIBUTE_UNUSED)
+ /* fprintf(stream, _("\
+ MicroBlaze options:\n\
+ -noSmall Data in the comm and data sections do not go into the small data section\n")); */
++ fprintf (stream, _(" MicroBlaze specific assembler options:\n"));
++ fprintf (stream, " -%-23s%s\n", "mbig-endian", N_("assemble for a big endian cpu"));
++ fprintf (stream, " -%-23s%s\n", "mlittle-endian", N_("assemble for a little endian cpu"));
+ }
+
+
diff --git a/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0003-Disable-the-warning-message-for-eh_frame_hdr.patch b/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0003-Disable-the-warning-message-for-eh_frame_hdr.patch
new file mode 100644
index 0000000..2b30c46
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0003-Disable-the-warning-message-for-eh_frame_hdr.patch
@@ -0,0 +1,34 @@
+From dac72d809be9faf9380b181df0c19a2c6d744c54 Mon Sep 17 00:00:00 2001
+From: "Edgar E. Iglesias" <edgar.iglesias at gmail.com>
+Date: Mon, 28 Aug 2017 19:53:54 -0700
+Subject: [PATCH] Disable the warning message for eh_frame_hdr
+
+Signed-off-by: Edgar E. Iglesias <edgar.iglesias at gmail.com>
+Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha at xilinx.com>
+Upstream-Status: Inappropriate [workaround]
+
+---
+ bfd/elf-eh-frame.c | 9 ++++++---
+ 1 file changed, 6 insertions(+), 3 deletions(-)
+
+diff --git a/bfd/elf-eh-frame.c b/bfd/elf-eh-frame.c
+index 95697c4..704121d 100644
+--- a/bfd/elf-eh-frame.c
++++ b/bfd/elf-eh-frame.c
+@@ -1042,10 +1042,13 @@ _bfd_elf_parse_eh_frame (bfd *abfd, struct bfd_link_info *info,
+ goto success;
+
+ free_no_table:
+- (*info->callbacks->einfo)
++ /* FIXME: Remove the microblaze specifics when relaxing gets fixed. */
++ if (bfd_get_arch(abfd) != bfd_arch_microblaze) {
+ /* xgettext:c-format */
+- (_("%P: error in %B(%A); no .eh_frame_hdr table will be created.\n"),
+- abfd, sec);
++ (*info->callbacks->einfo)
++ (_("%P: error in %B(%A); no .eh_frame_hdr table will be created.\n"),
++ abfd, sec);
++ }
+ hdr_info->u.dwarf.table = FALSE;
+ if (sec_info)
+ free (sec_info);
diff --git a/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0004-Fix-relaxation-of-assembler-resolved-references.patch b/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0004-Fix-relaxation-of-assembler-resolved-references.patch
new file mode 100644
index 0000000..b543c54
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0004-Fix-relaxation-of-assembler-resolved-references.patch
@@ -0,0 +1,81 @@
+From 927ef228dfedf229dc915b273a308ab2c7bf9e19 Mon Sep 17 00:00:00 2001
+From: "Edgar E. Iglesias" <edgar.iglesias at gmail.com>
+Date: Mon, 28 Aug 2017 19:53:55 -0700
+Subject: [PATCH] Fix relaxation of assembler resolved references
+
+03/2018
+Rebased for binutils 2.30
+
+Signed-off-by: Edgar E. Iglesias <edgar.iglesias at gmail.com>
+Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha at xilinx.com>
+Signed-off-by: Alejandro Enedino Hernandez Samaniego <alejandr at xilinx.com>
+
+Upstream-Status: Pending
+
+---
+ bfd/elf32-microblaze.c | 39 +++++++++++++++++++++++++++++++++++++++
+ gas/config/tc-microblaze.c | 1 +
+ 2 files changed, 40 insertions(+)
+
+diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c
+index f1808bc..a1d810c 100644
+--- a/bfd/elf32-microblaze.c
++++ b/bfd/elf32-microblaze.c
+@@ -1887,6 +1887,45 @@ microblaze_elf_relax_section (bfd *abfd,
+ irelscanend = irelocs + o->reloc_count;
+ for (irelscan = irelocs; irelscan < irelscanend; irelscan++)
+ {
++ if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_NONE)
++ {
++ unsigned int val;
++
++ isym = isymbuf + ELF32_R_SYM (irelscan->r_info);
++
++ /* This was a PC-relative instruction that was completely resolved. */
++ if (ocontents == NULL)
++ {
++ if (elf_section_data (o)->this_hdr.contents != NULL)
++ ocontents = elf_section_data (o)->this_hdr.contents;
++ else
++ {
++ /* We always cache the section contents.
++ Perhaps, if info->keep_memory is FALSE, we
++ should free them, if we are permitted to. */
++
++ if (o->rawsize == 0)
++ o->rawsize = o->size;
++ ocontents = (bfd_byte *) bfd_malloc (o->rawsize);
++ if (ocontents == NULL)
++ goto error_return;
++ if (!bfd_get_section_contents (abfd, o, ocontents,
++ (file_ptr) 0,
++ o->rawsize))
++ goto error_return;
++ elf_section_data (o)->this_hdr.contents = ocontents;
++ }
++ }
++
++ irelscan->r_addend -= calc_fixup (irelscan->r_addend
++ + isym->st_value, sec);
++ val = bfd_get_32 (abfd, ocontents + irelscan->r_offset);
++ microblaze_bfd_write_imm_value_32 (abfd, ocontents + irelscan->r_offset,
++ irelscan->r_addend);
++ }
++ if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_64_NONE) {
++ fprintf(stderr, "Unhandled NONE 64\n");
++ }
+ if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32)
+ {
+ isym = isymbuf + ELF32_R_SYM (irelscan->r_info);
+diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
+index 42dd7ae..50dbfc7 100644
+--- a/gas/config/tc-microblaze.c
++++ b/gas/config/tc-microblaze.c
+@@ -2183,6 +2183,7 @@ md_apply_fix (fixS * fixP,
+ else
+ fixP->fx_r_type = BFD_RELOC_NONE;
+ fixP->fx_addsy = section_symbol (absolute_section);
++ fixP->fx_done = 0;
+ }
+ return;
+ }
diff --git a/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0005-Fixup-MicroBlaze-debug_loc-sections-after-linker-rel.patch b/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0005-Fixup-MicroBlaze-debug_loc-sections-after-linker-rel.patch
new file mode 100644
index 0000000..3817234
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0005-Fixup-MicroBlaze-debug_loc-sections-after-linker-rel.patch
@@ -0,0 +1,242 @@
+From 5bf68bc39976903929f730b6eed18686c3563c05 Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nagaraju.mekala at xilinx.com>
+Date: Mon, 28 Aug 2017 19:53:56 -0700
+Subject: [PATCH] Fixup MicroBlaze debug_loc sections after linker relaxation
+
+Fixup debug_loc sections after linker relaxation Adds a new reloctype
+R_MICROBLAZE_32_NONE, used for passing reloc info from the assembler to
+the linker when the linker manages to fully resolve a local symbol
+reference.
+
+This is a workaround for design flaws in the assembler to
+linker interface with regards to linker relaxation.
+
+03/2018
+Rebased for binutils 2.30
+
+Signed-off-by: Edgar E. Iglesias <edgar.iglesias at gmail.com>
+Signed-off-by: Nagaraju Mekala <nmekala at xilinx.com>
+Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha at xilinx.com>
+Signed-off-by: Alejandro Enedino Hernandez Samaniego <alejandr at xilinx.com>
+
+Upstream-Status: Pending
+
+---
+ bfd/bfd-in2.h | 9 +++++++--
+ bfd/elf32-microblaze.c | 45 ++++++++++++++++++++++++++++++++++++++-------
+ bfd/libbfd.h | 1 +
+ bfd/reloc.c | 6 ++++++
+ binutils/readelf.c | 4 ++++
+ gas/config/tc-microblaze.c | 5 ++++-
+ include/elf/microblaze.h | 1 +
+ 7 files changed, 61 insertions(+), 10 deletions(-)
+
+diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
+index 4228603..1906195 100644
+--- a/bfd/bfd-in2.h
++++ b/bfd/bfd-in2.h
+@@ -5826,10 +5826,15 @@ value relative to the read-write small data area anchor */
+ expressions of the form "Symbol Op Symbol" */
+ BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM,
+
+-/* This is a 64 bit reloc that stores the 32 bit pc relative
++/* This is a 32 bit reloc that stores the 32 bit pc relative
+ value in two words (with an imm instruction). No relocation is
+ done here - only used for relaxing */
+- BFD_RELOC_MICROBLAZE_64_NONE,
++ BFD_RELOC_MICROBLAZE_32_NONE,
++
++/* This is a 64 bit reloc that stores the 32 bit pc relative
++ * +value in two words (with an imm instruction). No relocation is
++ * +done here - only used for relaxing */
++ BFD_RELOC_MICROBLAZE_64_NONE,
+
+ /* This is a 64 bit reloc that stores the 32 bit pc relative
+ value in two words (with an imm instruction). The relocation is
+diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c
+index a1d810c..fc0d3e1 100644
+--- a/bfd/elf32-microblaze.c
++++ b/bfd/elf32-microblaze.c
+@@ -176,6 +176,20 @@ static reloc_howto_type microblaze_elf_howto_raw[] =
+ 0x0000ffff, /* Dest Mask. */
+ FALSE), /* PC relative offset? */
+
++ HOWTO (R_MICROBLAZE_32_NONE, /* Type. */
++ 0, /* Rightshift. */
++ 2, /* Size (0 = byte, 1 = short, 2 = long). */
++ 32, /* Bitsize. */
++ TRUE, /* PC_relative. */
++ 0, /* Bitpos. */
++ complain_overflow_bitfield, /* Complain on overflow. */
++ NULL, /* Special Function. */
++ "R_MICROBLAZE_32_NONE",/* Name. */
++ FALSE, /* Partial Inplace. */
++ 0, /* Source Mask. */
++ 0, /* Dest Mask. */
++ FALSE), /* PC relative offset? */
++
+ /* This reloc does nothing. Used for relaxation. */
+ HOWTO (R_MICROBLAZE_64_NONE, /* Type. */
+ 0, /* Rightshift. */
+@@ -532,6 +546,9 @@ microblaze_elf_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED,
+ case BFD_RELOC_NONE:
+ microblaze_reloc = R_MICROBLAZE_NONE;
+ break;
++ case BFD_RELOC_MICROBLAZE_32_NONE:
++ microblaze_reloc = R_MICROBLAZE_32_NONE;
++ break;
+ case BFD_RELOC_MICROBLAZE_64_NONE:
+ microblaze_reloc = R_MICROBLAZE_64_NONE;
+ break;
+@@ -1832,14 +1849,23 @@ microblaze_elf_relax_section (bfd *abfd,
+ }
+ break;
+ case R_MICROBLAZE_NONE:
++ case R_MICROBLAZE_32_NONE:
+ {
+ /* This was a PC-relative instruction that was
+ completely resolved. */
+ int sfix, efix;
++ unsigned int val;
+ bfd_vma target_address;
+ target_address = irel->r_addend + irel->r_offset;
+ sfix = calc_fixup (irel->r_offset, 0, sec);
+ efix = calc_fixup (target_address, 0, sec);
++
++ /* Validate the in-band val. */
++ val = bfd_get_32 (abfd, contents + irel->r_offset);
++ if (val != irel->r_addend && ELF32_R_TYPE (irel->r_info) == R_MICROBLAZE_32_NONE) {
++ fprintf(stderr, "%d: CORRUPT relax reloc %x %lx\n", __LINE__, val, irel->r_addend);
++ }
++
+ irel->r_addend -= (efix - sfix);
+ /* Should use HOWTO. */
+ microblaze_bfd_write_imm_value_32 (abfd, contents + irel->r_offset,
+@@ -1887,12 +1913,16 @@ microblaze_elf_relax_section (bfd *abfd,
+ irelscanend = irelocs + o->reloc_count;
+ for (irelscan = irelocs; irelscan < irelscanend; irelscan++)
+ {
+- if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_NONE)
++ if (1 && ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32_NONE)
+ {
+ unsigned int val;
+
+ isym = isymbuf + ELF32_R_SYM (irelscan->r_info);
+
++ /* hax: We only do the following fixup for debug location lists. */
++ if (strcmp(".debug_loc", o->name))
++ continue;
++
+ /* This was a PC-relative instruction that was completely resolved. */
+ if (ocontents == NULL)
+ {
+@@ -1917,15 +1947,16 @@ microblaze_elf_relax_section (bfd *abfd,
+ }
+ }
+
+- irelscan->r_addend -= calc_fixup (irelscan->r_addend
+- + isym->st_value, sec);
+ val = bfd_get_32 (abfd, ocontents + irelscan->r_offset);
++
++ if (val != irelscan->r_addend) {
++ fprintf(stderr, "%d: CORRUPT relax reloc! %x %lx\n", __LINE__, val, irelscan->r_addend);
++ }
++ irelscan->r_addend -= calc_fixup (irelscan->r_addend, 0, sec);
++
+ microblaze_bfd_write_imm_value_32 (abfd, ocontents + irelscan->r_offset,
+ irelscan->r_addend);
+ }
+- if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_64_NONE) {
+- fprintf(stderr, "Unhandled NONE 64\n");
+- }
+ if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32)
+ {
+ isym = isymbuf + ELF32_R_SYM (irelscan->r_info);
+@@ -1985,7 +2016,7 @@ microblaze_elf_relax_section (bfd *abfd,
+ elf_section_data (o)->this_hdr.contents = ocontents;
+ }
+ }
+- irelscan->r_addend -= calc_fixup (irel->r_addend
++ irelscan->r_addend -= calc_fixup (irelscan->r_addend
+ + isym->st_value,
+ 0,
+ sec);
+diff --git a/bfd/libbfd.h b/bfd/libbfd.h
+index 2f5f16e..854bb0c 100644
+--- a/bfd/libbfd.h
++++ b/bfd/libbfd.h
+@@ -2853,6 +2853,7 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",
+ "BFD_RELOC_MICROBLAZE_32_ROSDA",
+ "BFD_RELOC_MICROBLAZE_32_RWSDA",
+ "BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM",
++ "BFD_RELOC_MICROBLAZE_32_NONE",
+ "BFD_RELOC_MICROBLAZE_64_NONE",
+ "BFD_RELOC_MICROBLAZE_64_GOTPC",
+ "BFD_RELOC_MICROBLAZE_64_GOT",
+diff --git a/bfd/reloc.c b/bfd/reloc.c
+index a1353a2..4b57de7 100644
+--- a/bfd/reloc.c
++++ b/bfd/reloc.c
+@@ -6903,6 +6903,12 @@ ENUMDOC
+ This is a 32 bit reloc for the microblaze to handle
+ expressions of the form "Symbol Op Symbol"
+ ENUM
++ BFD_RELOC_MICROBLAZE_32_NONE
++ENUMDOC
++ This is a 32 bit reloc that stores the 32 bit pc relative
++ value in two words (with an imm instruction). No relocation is
++ done here - only used for relaxing
++ENUM
+ BFD_RELOC_MICROBLAZE_64_NONE
+ ENUMDOC
+ This is a 64 bit reloc that stores the 32 bit pc relative
+diff --git a/binutils/readelf.c b/binutils/readelf.c
+index fed0387..92f655d 100644
+--- a/binutils/readelf.c
++++ b/binutils/readelf.c
+@@ -12774,6 +12774,10 @@ is_none_reloc (Filedata * filedata, unsigned int reloc_type)
+ || reloc_type == 32 /* R_AVR_DIFF32. */);
+ case EM_METAG:
+ return reloc_type == 3; /* R_METAG_NONE. */
++ case EM_MICROBLAZE:
++ return reloc_type == 30 /* R_MICROBLAZE_32_NONE. */
++ || reloc_type == 0 /* R_MICROBLAZE_NONE. */
++ || reloc_type == 9; /* R_MICROBLAZE_64_NONE. */
+ case EM_NDS32:
+ return (reloc_type == 0 /* R_XTENSA_NONE. */
+ || reloc_type == 204 /* R_NDS32_DIFF8. */
+diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
+index 50dbfc7..d66e949 100644
+--- a/gas/config/tc-microblaze.c
++++ b/gas/config/tc-microblaze.c
+@@ -2179,7 +2179,9 @@ md_apply_fix (fixS * fixP,
+ /* This fixup has been resolved. Create a reloc in case the linker
+ moves code around due to relaxing. */
+ if (fixP->fx_r_type == BFD_RELOC_64_PCREL)
+- fixP->fx_r_type = BFD_RELOC_MICROBLAZE_64_NONE;
++ fixP->fx_r_type = BFD_RELOC_MICROBLAZE_64_NONE;
++ else if (fixP->fx_r_type == BFD_RELOC_32)
++ fixP->fx_r_type = BFD_RELOC_MICROBLAZE_32_NONE;
+ else
+ fixP->fx_r_type = BFD_RELOC_NONE;
+ fixP->fx_addsy = section_symbol (absolute_section);
+@@ -2401,6 +2403,7 @@ tc_gen_reloc (asection * section ATTRIBUTE_UNUSED, fixS * fixp)
+ switch (fixp->fx_r_type)
+ {
+ case BFD_RELOC_NONE:
++ case BFD_RELOC_MICROBLAZE_32_NONE:
+ case BFD_RELOC_MICROBLAZE_64_NONE:
+ case BFD_RELOC_32:
+ case BFD_RELOC_MICROBLAZE_32_LO:
+diff --git a/include/elf/microblaze.h b/include/elf/microblaze.h
+index ae98099..c8cc57b 100644
+--- a/include/elf/microblaze.h
++++ b/include/elf/microblaze.h
+@@ -58,6 +58,7 @@ START_RELOC_NUMBERS (elf_microblaze_reloc_type)
+ RELOC_NUMBER (R_MICROBLAZE_TLSDTPREL64, 27) /* TLS Offset Within TLS Block */
+ RELOC_NUMBER (R_MICROBLAZE_TLSGOTTPREL32, 28) /* TLS Offset From Thread Pointer */
+ RELOC_NUMBER (R_MICROBLAZE_TLSTPREL32, 29) /* TLS Offset From Thread Pointer */
++ RELOC_NUMBER (R_MICROBLAZE_32_NONE, 30)
+
+ END_RELOC_NUMBERS (R_MICROBLAZE_max)
+
diff --git a/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0006-Fix-bug-in-MicroBlaze-TLSTPREL-Relocation.patch b/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0006-Fix-bug-in-MicroBlaze-TLSTPREL-Relocation.patch
new file mode 100644
index 0000000..a671cf8
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0006-Fix-bug-in-MicroBlaze-TLSTPREL-Relocation.patch
@@ -0,0 +1,35 @@
+From 0cad227ce495a975b32c10a8b6b0970c45024dd6 Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nagaraju.mekala at xilinx.com>
+Date: Mon, 28 Aug 2017 19:53:58 -0700
+Subject: [PATCH] Fix bug in MicroBlaze TLSTPREL Relocation
+
+Fixed the problem related to the fixup/relocations TLSTPREL.
+When the fixup is applied the addend is not added at the correct offset
+of the instruction. The offset is hard coded considering its big endian
+and it fails for Little endian. This patch allows support for both
+big & little-endian compilers
+
+Signed-off-by: Nagaraju Mekala <nagaraju.mekala at xilinx.com>
+Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha at xilinx.com>
+Upstream-Status: Pending
+
+---
+ bfd/elf32-microblaze.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c
+index fc0d3e1..a94799f 100644
+--- a/bfd/elf32-microblaze.c
++++ b/bfd/elf32-microblaze.c
+@@ -1402,9 +1402,9 @@ microblaze_elf_relocate_section (bfd *output_bfd,
+ relocation += addend;
+ relocation -= dtprel_base(info);
+ bfd_put_16 (input_bfd, (relocation >> 16) & 0xffff,
+- contents + offset + 2);
++ contents + offset + endian);
+ bfd_put_16 (input_bfd, relocation & 0xffff,
+- contents + offset + 2 + INST_WORD_SIZE);
++ contents + offset + endian + INST_WORD_SIZE);
+ break;
+ case (int) R_MICROBLAZE_64_PCREL :
+ case (int) R_MICROBLAZE_64:
diff --git a/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0007-Add-MicroBlaze-address-extension-instructions.patch b/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0007-Add-MicroBlaze-address-extension-instructions.patch
new file mode 100644
index 0000000..9672c51
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0007-Add-MicroBlaze-address-extension-instructions.patch
@@ -0,0 +1,104 @@
+From 3895968b5c55321d203cadb7630a2baee8699e17 Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nagaraju.mekala at xilinx.com>
+Date: Mon, 28 Aug 2017 19:53:59 -0700
+Subject: [PATCH] Add MicroBlaze address extension instructions
+
+This patch adds the support of new instructions which are required
+for supporting Address extension feature.
+
+2016-01-18 Nagaraju Mekala <nagaraju.mekala at xilinx.com>
+
+ * microblaze-opc.h (op_code_struct): Added new instructions
+ * microblaze-opcm.h (microblaze_instr): Added new instructions
+
+Signed-off-by: Nagaraju Mekala <nagaraju.mekala at xilinx.com>
+Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha at xilinx.com>
+Upstream-Status: Pending
+
+---
+ opcodes/microblaze-opc.h | 13 ++++++++++++-
+ opcodes/microblaze-opcm.h | 10 +++++-----
+ 2 files changed, 17 insertions(+), 6 deletions(-)
+
+diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
+index 773dc81..4e69f76 100644
+--- a/opcodes/microblaze-opc.h
++++ b/opcodes/microblaze-opc.h
+@@ -102,7 +102,7 @@
+ #define DELAY_SLOT 1
+ #define NO_DELAY_SLOT 0
+
+-#define MAX_OPCODES 291
++#define MAX_OPCODES 299
+
+ struct op_code_struct
+ {
+@@ -178,8 +178,11 @@ struct op_code_struct
+ {"wdc.ext.clear", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000466, OPCODE_MASK_H35B, wdcextclear, special_inst },
+ {"wdc.flush", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000074, OPCODE_MASK_H34B, wdcflush, special_inst },
+ {"wdc.ext.flush", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000476, OPCODE_MASK_H35B, wdcextflush, special_inst },
++ {"wdc.clear.ea", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900000E6, OPCODE_MASK_H34B, wdcclearea, special_inst },
+ {"mts", INST_TYPE_SPECIAL_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MTS, 0x9400C000, OPCODE_MASK_H13S, mts, special_inst },
++ {"mtse", INST_TYPE_SPECIAL_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MTS, 0x9500C000, OPCODE_MASK_H13S, mtse,special_inst },
+ {"mfs", INST_TYPE_RD_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MFS, 0x94008000, OPCODE_MASK_H23S, mfs, special_inst },
++ {"mfse", INST_TYPE_RD_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MFS, 0x94088000, OPCODE_MASK_H23S, mfse, special_inst },
+ {"br", INST_TYPE_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98000000, OPCODE_MASK_H124, br, branch_inst },
+ {"brd", INST_TYPE_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98100000, OPCODE_MASK_H124, brd, branch_inst },
+ {"brld", INST_TYPE_RD_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98140000, OPCODE_MASK_H24, brld, branch_inst },
+@@ -229,18 +232,24 @@ struct op_code_struct
+ {"bgeid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBEA00000, OPCODE_MASK_H1, bgeid, branch_inst },
+ {"lbu", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC0000000, OPCODE_MASK_H4, lbu, memory_load_inst },
+ {"lbur", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC0000200, OPCODE_MASK_H4, lbur, memory_load_inst },
++ {"lbuea", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC0000080, OPCODE_MASK_H4, lbuea, memory_load_inst },
+ {"lhu", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC4000000, OPCODE_MASK_H4, lhu, memory_load_inst },
+ {"lhur", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC4000200, OPCODE_MASK_H4, lhur, memory_load_inst },
++ {"lhuea", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC4000080, OPCODE_MASK_H4, lhuea, memory_load_inst },
+ {"lw", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000000, OPCODE_MASK_H4, lw, memory_load_inst },
+ {"lwr", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000200, OPCODE_MASK_H4, lwr, memory_load_inst },
+ {"lwx", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000400, OPCODE_MASK_H4, lwx, memory_load_inst },
++ {"lwea", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000080, OPCODE_MASK_H4, lwea, memory_load_inst },
+ {"sb", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD0000000, OPCODE_MASK_H4, sb, memory_store_inst },
+ {"sbr", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD0000200, OPCODE_MASK_H4, sbr, memory_store_inst },
++ {"sbea", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD0000080, OPCODE_MASK_H4, sbea, memory_store_inst },
+ {"sh", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD4000000, OPCODE_MASK_H4, sh, memory_store_inst },
+ {"shr", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD4000200, OPCODE_MASK_H4, shr, memory_store_inst },
++ {"shea", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD4000080, OPCODE_MASK_H4, shea, memory_store_inst },
+ {"sw", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000000, OPCODE_MASK_H4, sw, memory_store_inst },
+ {"swr", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000200, OPCODE_MASK_H4, swr, memory_store_inst },
+ {"swx", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000400, OPCODE_MASK_H4, swx, memory_store_inst },
++ {"swea", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000080, OPCODE_MASK_H4, swea, memory_store_inst },
+ {"lbui", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE0000000, OPCODE_MASK_H, lbui, memory_load_inst },
+ {"lhui", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE4000000, OPCODE_MASK_H, lhui, memory_load_inst },
+ {"lwi", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE8000000, OPCODE_MASK_H, lwi, memory_load_inst },
+@@ -405,6 +414,8 @@ struct op_code_struct
+ {"clz", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900000E0, OPCODE_MASK_H34, clz, special_inst },
+ {"mbar", INST_TYPE_IMM5, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8020004, OPCODE_MASK_HN, mbar, special_inst },
+ {"sleep", INST_TYPE_NONE, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBA020004, OPCODE_MASK_HN, invalid_inst, special_inst }, /* translates to mbar 16. */
++ {"hibernate", INST_TYPE_NONE, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB9020004, OPCODE_MASK_HN, invalid_inst, special_inst }, /* translates to mbar 8. */
++ {"suspend", INST_TYPE_NONE, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBB020004, OPCODE_MASK_HN, invalid_inst, special_inst }, /* translates to mbar 24. */
+ {"swapb", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900001E0, OPCODE_MASK_H4, swapb, arithmetic_inst },
+ {"swaph", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900001E2, OPCODE_MASK_H4, swaph, arithmetic_inst },
+ {"", 0, 0, 0, 0, 0, 0, 0, 0},
+diff --git a/opcodes/microblaze-opcm.h b/opcodes/microblaze-opcm.h
+index 7338f6a..c75f10a 100644
+--- a/opcodes/microblaze-opcm.h
++++ b/opcodes/microblaze-opcm.h
+@@ -33,13 +33,13 @@ enum microblaze_instr
+ /* 'or/and/xor' are C++ keywords. */
+ microblaze_or, microblaze_and, microblaze_xor,
+ andn, pcmpbf, pcmpbc, pcmpeq, pcmpne, sra, src, srl, sext8, sext16,
+- wic, wdc, wdcclear, wdcextclear, wdcflush, wdcextflush, mts, mfs, mbar, br,
+- brd, brld, bra, brad, brald, microblaze_brk, beq, beqd, bne, bned, blt,
+- bltd, ble, bled, bgt, bgtd, bge, bged, ori, andi, xori, andni,
++ wic, wdc, wdcclear, wdcextclear, wdcflush, wdcextflush, wdcclearea, mts, mtse,
++ mfs, mfse, mbar, br, brd, brld, bra, brad, brald, microblaze_brk, beq, beqd,
++ bne, bned, blt, bltd, ble, bled, bgt, bgtd, bge, bged, ori, andi, xori, andni,
+ imm, rtsd, rtid, rtbd, rted, bri, brid, brlid, brai, braid, bralid,
+ brki, beqi, beqid, bnei, bneid, blti, bltid, blei, bleid, bgti,
+- bgtid, bgei, bgeid, lbu, lbur, lhu, lhur, lw, lwr, lwx, sb, sbr, sh,
+- shr, sw, swr, swx, lbui, lhui, lwi,
++ bgtid, bgei, bgeid, lbu, lbuea, lbur, lhu, lhuea, lhur, lw, lwea, lwr, lwx,
++ sb, sbea, sbr, sh, shea, shr, sw, swea, swr, swx, lbui, lhui, lwi,
+ sbi, shi, swi, msrset, msrclr, tuqula, fadd, frsub, fmul, fdiv,
+ fcmp_lt, fcmp_eq, fcmp_le, fcmp_gt, fcmp_ne, fcmp_ge, fcmp_un, flt,
+ fint, fsqrt,
diff --git a/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0008-Add-new-MicroBlaze-bit-field-instructions.patch b/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0008-Add-new-MicroBlaze-bit-field-instructions.patch
new file mode 100644
index 0000000..0bc0117
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0008-Add-new-MicroBlaze-bit-field-instructions.patch
@@ -0,0 +1,232 @@
+From 5c4dacaae2ba93569c1d37cda9859c57d6649dc0 Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nagaraju.mekala at xilinx.com>
+Date: Mon, 28 Aug 2017 19:54:01 -0700
+Subject: [PATCH] Add new MicroBlaze bit-field instructions
+
+This patches adds new bsefi and bsifi instructions. BSEFI- The
+instruction shall extract a bit field from a register and place it
+right-adjusted in the destination register. The other bits in the
+destination register shall be set to zero BSIFI- The instruction shall
+insert a right-adjusted bit field from a register at another position in
+the destination register. The rest of the bits in the destination
+register shall be unchanged
+
+Signed-off-by: Nagaraju Mekala <nagaraju.mekala at xilinx.com>
+Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha at xilinx.com>
+Upstream-Status: Pending
+---
+ gas/config/tc-microblaze.c | 71 +++++++++++++++++++++++++++++++++++++++++++++-
+ opcodes/microblaze-dis.c | 16 +++++++++++
+ opcodes/microblaze-opc.h | 12 +++++++-
+ opcodes/microblaze-opcm.h | 6 +++-
+ 4 files changed, 102 insertions(+), 3 deletions(-)
+
+diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
+index e135547e62..34cb80fac2 100644
+--- a/gas/config/tc-microblaze.c
++++ b/gas/config/tc-microblaze.c
+@@ -909,7 +909,7 @@ md_assemble (char * str)
+ unsigned reg2;
+ unsigned reg3;
+ unsigned isize;
+- unsigned int immed, temp;
++ unsigned int immed, immed2, temp;
+ expressionS exp;
+ char name[20];
+
+@@ -1164,7 +1164,76 @@ md_assemble (char * str)
+ inst |= (reg2 << RA_LOW) & RA_MASK;
+ inst |= (immed << IMM_LOW) & IMM5_MASK;
+ break;
++ case INST_TYPE_RD_R1_IMM5_IMM5:
++ if (strcmp (op_end, ""))
++ op_end = parse_reg (op_end + 1, ®1); /* Get rd. */
++ else
++ {
++ as_fatal (_("Error in statement syntax"));
++ reg1 = 0;
++ }
++ if (strcmp (op_end, ""))
++ op_end = parse_reg (op_end + 1, ®2); /* Get r1. */
++ else
++ {
++ as_fatal (_("Error in statement syntax"));
++ reg2 = 0;
++ }
++
++ /* Check for spl registers. */
++ if (check_spl_reg (®1))
++ as_fatal (_("Cannot use special register with this instruction"));
++ if (check_spl_reg (®2))
++ as_fatal (_("Cannot use special register with this instruction"));
+
++ /* Width immediate value. */
++ if (strcmp (op_end, ""))
++ op_end = parse_imm (op_end + 1, &exp, MIN_IMM_WIDTH, MAX_IMM_WIDTH);
++ else
++ as_fatal (_("Error in statement syntax"));
++ if (exp.X_op != O_constant)
++ {
++ as_warn (_("Symbol used as immediate width value for bit field instruction"));
++ immed = 1;
++ }
++ else
++ immed = exp.X_add_number;
++ if (opcode->instr == bsefi && immed > 31)
++ as_fatal (_("Width value must be less than 32"));
++
++ /* Shift immediate value. */
++ if (strcmp (op_end, ""))
++ op_end = parse_imm (op_end + 1, &exp, MIN_IMM, MAX_IMM);
++ else
++ as_fatal (_("Error in statement syntax"));
++ if (exp.X_op != O_constant)
++ {
++ as_warn (_("Symbol used as immediate shift value for bit field instruction"));
++ immed2 = 0;
++ }
++ else
++ {
++ output = frag_more (isize);
++ immed2 = exp.X_add_number;
++ }
++ if (immed2 != (immed2 % 32))
++ {
++ as_warn (_("Shift value greater than 32. using <value %% 32>"));
++ immed2 = immed2 % 32;
++ }
++
++ /* Check combined value. */
++ if (immed + immed2 > 32)
++ as_fatal (_("Width value + shift value must not be greater than 32"));
++
++ inst |= (reg1 << RD_LOW) & RD_MASK;
++ inst |= (reg2 << RA_LOW) & RA_MASK;
++ if (opcode->instr == bsefi)
++ inst |= (immed & IMM5_MASK) << IMM_WIDTH_LOW; /* bsefi */
++ else
++ inst |= ((immed + immed2 - 1) & IMM5_MASK) << IMM_WIDTH_LOW; /* bsifi */
++ inst |= (immed2 << IMM_LOW) & IMM5_MASK;
++ break;
+ case INST_TYPE_R1_R2:
+ if (strcmp (op_end, ""))
+ op_end = parse_reg (op_end + 1, ®1); /* Get r1. */
+diff --git a/opcodes/microblaze-dis.c b/opcodes/microblaze-dis.c
+index 6a174b0eb9..80a47ad2fc 100644
+--- a/opcodes/microblaze-dis.c
++++ b/opcodes/microblaze-dis.c
+@@ -73,6 +73,18 @@ get_field_imm5_mbar (long instr)
+ return(strdup(tmpstr));
+ }
+
++static char *
++get_field_imm5width (long instr)
++{
++ char tmpstr[25];
++
++ if (instr & 0x00004000)
++ sprintf (tmpstr, "%d", (short)(((instr & IMM5_WIDTH_MASK) >> IMM_WIDTH_LOW))); /* bsefi */
++ else
++ sprintf (tmpstr, "%d", (short)(((instr & IMM5_WIDTH_MASK) >> IMM_WIDTH_LOW) - ((instr & IMM5_MASK) >> IMM_LOW) + 1)); /* bsifi */
++ return (strdup (tmpstr));
++}
++
+ static char *
+ get_field_rfsl (long instr)
+ {
+@@ -396,6 +408,10 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info)
+ /* For mbar 16 or sleep insn. */
+ case INST_TYPE_NONE:
+ break;
++ /* For bit field insns. */
++ case INST_TYPE_RD_R1_IMM5_IMM5:
++ print_func (stream, "\t%s, %s, %s, %s", get_field_rd (inst),get_field_r1(inst),get_field_imm5width (inst), get_field_imm5 (inst));
++ break;
+ /* For tuqula instruction */
+ case INST_TYPE_RD:
+ print_func (stream, "\t%s", get_field_rd (inst));
+diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
+index a64f8362da..afb34989d9 100644
+--- a/opcodes/microblaze-opc.h
++++ b/opcodes/microblaze-opc.h
+@@ -59,6 +59,9 @@
+ /* For mbar. */
+ #define INST_TYPE_IMM5 20
+
++/* For bsefi and bsifi */
++#define INST_TYPE_RD_R1_IMM5_IMM5 21
++
+ #define INST_TYPE_NONE 25
+
+
+@@ -89,7 +92,9 @@
+ #define OPCODE_MASK_H124 0xFFFF07FF /* High 16, and low 11 bits. */
+ #define OPCODE_MASK_H1234 0xFFFFFFFF /* All 32 bits. */
+ #define OPCODE_MASK_H3 0xFC000600 /* High 6 bits and bits 21, 22. */
++#define OPCODE_MASK_H3B 0xFC00C600 /* High 6 bits and bits 16, 17, 21, 22. */
+ #define OPCODE_MASK_H32 0xFC00FC00 /* High 6 bits and bit 16-21. */
++#define OPCODE_MASK_H32B 0xFC00C000 /* High 6 bits and bit 16, 17. */
+ #define OPCODE_MASK_H34B 0xFC0000FF /* High 6 bits and low 8 bits. */
+ #define OPCODE_MASK_H35B 0xFC0004FF /* High 6 bits and low 9 bits. */
+ #define OPCODE_MASK_H34C 0xFC0007E0 /* High 6 bits and bits 21-26. */
+@@ -102,7 +107,7 @@
+ #define DELAY_SLOT 1
+ #define NO_DELAY_SLOT 0
+
+-#define MAX_OPCODES 299
++#define MAX_OPCODES 301
+
+ struct op_code_struct
+ {
+@@ -159,6 +164,8 @@ struct op_code_struct
+ {"bslli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000400, OPCODE_MASK_H3, bslli, barrel_shift_inst },
+ {"bsrai", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000200, OPCODE_MASK_H3, bsrai, barrel_shift_inst },
+ {"bsrli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000000, OPCODE_MASK_H3, bsrli, barrel_shift_inst },
++ {"bsefi", INST_TYPE_RD_R1_IMM5_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64004000, OPCODE_MASK_H32B, bsefi, barrel_shift_inst },
++ {"bsifi", INST_TYPE_RD_R1_IMM5_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64008000, OPCODE_MASK_H32B, bsifi, barrel_shift_inst },
+ {"or", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x80000000, OPCODE_MASK_H4, microblaze_or, logical_inst },
+ {"and", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x84000000, OPCODE_MASK_H4, microblaze_and, logical_inst },
+ {"xor", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x88000000, OPCODE_MASK_H4, microblaze_xor, logical_inst },
+@@ -438,5 +445,8 @@ char pvr_register_prefix[] = "rpvr";
+ #define MIN_IMM5 ((int) 0x00000000)
+ #define MAX_IMM5 ((int) 0x0000001f)
+
++#define MIN_IMM_WIDTH ((int) 0x00000001)
++#define MAX_IMM_WIDTH ((int) 0x00000020)
++
+ #endif /* MICROBLAZE_OPC */
+
+diff --git a/opcodes/microblaze-opcm.h b/opcodes/microblaze-opcm.h
+index 21a3dc8d76..dd6be7f65c 100644
+--- a/opcodes/microblaze-opcm.h
++++ b/opcodes/microblaze-opcm.h
+@@ -29,7 +29,7 @@ enum microblaze_instr
+ addi, rsubi, addic, rsubic, addik, rsubik, addikc, rsubikc, mul,
+ mulh, mulhu, mulhsu,swapb,swaph,
+ idiv, idivu, bsll, bsra, bsrl, get, put, nget, nput, cget, cput,
+- ncget, ncput, muli, bslli, bsrai, bsrli, mului,
++ ncget, ncput, muli, bslli, bsrai, bsrli, bsefi, bsifi, mului,
+ /* 'or/and/xor' are C++ keywords. */
+ microblaze_or, microblaze_and, microblaze_xor,
+ andn, pcmpbf, pcmpbc, pcmpeq, pcmpne, sra, src, srl, sext8, sext16,
+@@ -129,6 +129,7 @@ enum microblaze_instr_type
+ #define RB_LOW 11 /* Low bit for RB. */
+ #define IMM_LOW 0 /* Low bit for immediate. */
+ #define IMM_MBAR 21 /* low bit for mbar instruction. */
++#define IMM_WIDTH_LOW 6 /* Low bit for immediate width */
+
+ #define RD_MASK 0x03E00000
+ #define RA_MASK 0x001F0000
+@@ -141,6 +142,9 @@ enum microblaze_instr_type
+ /* Imm mask for mbar. */
+ #define IMM5_MBAR_MASK 0x03E00000
+
++/* Imm mask for extract/insert width. */
++#define IMM5_WIDTH_MASK 0x000007C0
++
+ /* FSL imm mask for get, put instructions. */
+ #define RFSL_MASK 0x000000F
+
+--
+2.15.0
+
diff --git a/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0009-Fixing-MicroBlaze-IMM-bug.patch b/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0009-Fixing-MicroBlaze-IMM-bug.patch
new file mode 100644
index 0000000..bb7e91c
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0009-Fixing-MicroBlaze-IMM-bug.patch
@@ -0,0 +1,29 @@
+From f649406ccaea992f3931e0d9ca9fbd6efb0c553b Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nagaraju.mekala at xilinx.com>
+Date: Mon, 28 Aug 2017 19:54:02 -0700
+Subject: [PATCH] Fixing MicroBlaze IMM bug
+
+Fixing the imm bug. with relax option imm -1 is also getting removed this is corrected now.
+
+Signed-off-by: Nagaraju Mekala <nagaraju.mekala at xilinx.com>
+Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha at xilinx.com>
+Upstream-Status: Pending
+
+---
+ bfd/elf32-microblaze.c | 3 +--
+ 1 file changed, 1 insertion(+), 2 deletions(-)
+
+diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c
+index a94799f..74b00d2 100644
+--- a/bfd/elf32-microblaze.c
++++ b/bfd/elf32-microblaze.c
+@@ -1789,8 +1789,7 @@ microblaze_elf_relax_section (bfd *abfd,
+ else
+ symval += irel->r_addend;
+
+- if ((symval & 0xffff8000) == 0
+- || (symval & 0xffff8000) == 0xffff8000)
++ if ((symval & 0xffff8000) == 0)
+ {
+ /* We can delete this instruction. */
+ sec->relax[sec->relax_count].addr = irel->r_offset;
diff --git a/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0010-Fixed-bug-in-GCC-so-that-it-will-support-.long-0U-an.patch b/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0010-Fixed-bug-in-GCC-so-that-it-will-support-.long-0U-an.patch
new file mode 100644
index 0000000..077343e
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0010-Fixed-bug-in-GCC-so-that-it-will-support-.long-0U-an.patch
@@ -0,0 +1,34 @@
+From e1bacaa7c1aa387f167afff74876c5acdffc39d9 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat at xilinx.com>
+Date: Wed, 15 Nov 2017 17:45:35 -0800
+Subject: [PATCH] Fixed bug in GCC so that it will support .long 0U and .long
+ 0u
+
+Signed-off-by: Mahesh Bodapati <mbodapat at xilinx.com>
+Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha at xilinx.com>
+Upstream-Status: Pending
+
+---
+ gas/expr.c | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+diff --git a/gas/expr.c b/gas/expr.c
+index 3e28af6..0b7cc76 100644
+--- a/gas/expr.c
++++ b/gas/expr.c
+@@ -810,6 +810,15 @@ operand (expressionS *expressionP, enum expr_mode mode)
+ break;
+ }
+ }
++ if ((*input_line_pointer == 'U') || (*input_line_pointer == 'u'))
++ {
++ input_line_pointer--;
++
++ integer_constant ((NUMBERS_WITH_SUFFIX || flag_m68k_mri)
++ ? 0 : 10,
++ expressionP);
++ break;
++ }
+ c = *input_line_pointer;
+ switch (c)
+ {
diff --git a/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0011-Fixing-MicroBlaze-constant-range-check-issue.patch b/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0011-Fixing-MicroBlaze-constant-range-check-issue.patch
new file mode 100644
index 0000000..244a7ad
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0011-Fixing-MicroBlaze-constant-range-check-issue.patch
@@ -0,0 +1,28 @@
+From 9393a3e346d2ccbb86761117260c1dd89070a507 Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nagaraju.mekala at xilinx.com>
+Date: Wed, 15 Nov 2017 17:45:34 -0800
+Subject: [PATCH] Fixing MicroBlaze constant range check issue
+
+Sample error: not in range ffffffff80000000..7fffffff, not ffffffff70000000
+
+Signed-off-by: Nagaraju Mekala <nagaraju.mekala at xilinx.com>
+Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha at xilinx.com>
+Upstream-Status: Pending
+
+---
+ gas/config/tc-microblaze.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
+index 21a5a0c..c614556 100644
+--- a/gas/config/tc-microblaze.c
++++ b/gas/config/tc-microblaze.c
+@@ -749,7 +749,7 @@ parse_imm (char * s, expressionS * e, offsetT min, offsetT max)
+ if ((e->X_add_number >> 31) == 1)
+ e->X_add_number |= -((addressT) (1U << 31));
+
+- if (e->X_add_number < min || e->X_add_number > max)
++ if ((int)e->X_add_number < min || (int)e->X_add_number > max)
+ {
+ as_fatal (_("operand must be absolute in range %lx..%lx, not %lx"),
+ (long) min, (long) max, (long) e->X_add_number);
diff --git a/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0012-MicroBlaze-fix-mask-for-barrel-shift-instructions.patch b/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0012-MicroBlaze-fix-mask-for-barrel-shift-instructions.patch
new file mode 100644
index 0000000..e340c50
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0012-MicroBlaze-fix-mask-for-barrel-shift-instructions.patch
@@ -0,0 +1,36 @@
+From 732b5a44a0a032da5ebb775b5df2ee2a36af988f Mon Sep 17 00:00:00 2001
+From: Nathan Rossi <nathan at nathanrossi.com>
+Date: Sun, 5 Nov 2017 22:17:39 +1000
+Subject: [PATCH] MicroBlaze fix mask for barrel shift instructions
+
+As of v10.0 the bsi (bslli/bsrai/bsrli/bsefi/bsifi) instructions have
+bits 16 and 17 defined as 'Insert' and 'Extract' respectively to support
+bit field insert/extract operations. For the bslli/bsrai/bsrli
+instructions these bits must be 0, as such update the opcode mask so
+that the bslli/bsrai/bsrli instructions do not also match the bsefi and
+bsifi instructions.
+
+Signed-off-by: Nathan Rossi <nathan at nathanrossi.com>
+Upstream-Status: Pending
+
+---
+ opcodes/microblaze-opc.h | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
+index 4bc400a..9482d81 100644
+--- a/opcodes/microblaze-opc.h
++++ b/opcodes/microblaze-opc.h
+@@ -161,9 +161,9 @@ struct op_code_struct
+ {"ncget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C006000, OPCODE_MASK_H32, ncget, anyware_inst },
+ {"ncput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00E000, OPCODE_MASK_H32, ncput, anyware_inst },
+ {"muli", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x60000000, OPCODE_MASK_H, muli, mult_inst },
+- {"bslli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000400, OPCODE_MASK_H3, bslli, barrel_shift_inst },
+- {"bsrai", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000200, OPCODE_MASK_H3, bsrai, barrel_shift_inst },
+- {"bsrli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000000, OPCODE_MASK_H3, bsrli, barrel_shift_inst },
++ {"bslli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000400, OPCODE_MASK_H3B, bslli, barrel_shift_inst },
++ {"bsrai", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000200, OPCODE_MASK_H3B, bsrai, barrel_shift_inst },
++ {"bsrli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000000, OPCODE_MASK_H3B, bsrli, barrel_shift_inst },
+ {"bsefi", INST_TYPE_RD_R1_IMM5_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64004000, OPCODE_MASK_H32B, bsefi, barrel_shift_inst },
+ {"bsifi", INST_TYPE_RD_R1_IMM5_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64008000, OPCODE_MASK_H32B, bsifi, barrel_shift_inst },
+ {"or", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x80000000, OPCODE_MASK_H4, microblaze_or, logical_inst },
--
2.7.4
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