[meta-xilinx] linux-xlnx: wrong spi-nor eraseblock size

[Naga Sureshkumar Relli]

Hi Kevin,

Thanks for your observations on this erase size update.
Yes, in 2018.1 release the device erase size was incorrect for dual parallel configuration.
We fixed that in 2018.2 release. Once it is released you will have that fix.
You can use the attached patch to fix that now.

Thanks,
Naga Sureshkumar Relli

> -----Original Message-----
> From: Vineeth Chowdary [mailto:vineeth.chowdary at xilinx.com]
> Sent: Tuesday, May 22, 2018 2:51 PM
> To: Kevin Kruse <kkruse at integretek.com>; Naga Sureshkumar Relli
> <nagasure at xilinx.com>
> Cc: meta-xilinx at yoctoproject.org
> Subject: Re: [meta-xilinx] linux-xlnx: wrong spi-nor eraseblock size
> 
> Adding on latest one, Suresh, xlnx
> 
> On Mon, May 21, 2018 at 06:56:34PM +0000, Kevin Kruse wrote:
> > Update: I've confirmed the ZCU102 also shows an incorrect eraseblock size when built with
> the meta-xilinx 2018.1 layer. I'm able to fix the problem by reverting the following files to our
> custom-patched version of 2017.3's kernel sources. I'll submit a patch for 2018.1 once I've
> isolated the problem.
> >
> >
> > drivers/mtd/devices/m25p80.c
> >
> > drivers/mtd/spi-nor/spi-nor.c
> >
> > include/linux/mtd/spi-nor.h
> >
> >
> > Kevin Kruse
> > Design Engineer
> > Integre Technologies, LLC
> >
> > ________________________________
> > From: meta-xilinx-bounces at yoctoproject.org <meta-xilinx-bounces at yoctoproject.org> on
> behalf of Kevin Kruse <kkruse at integretek.com>
> > Sent: Friday, May 18, 2018 11:06:26 AM
> > To: meta-xilinx at yoctoproject.org
> > Subject: [meta-xilinx] linux-xlnx: wrong spi-nor eraseblock size
> >
> >
> > I created a custom board similar to the ZCU102. I'm unable to flash a UBIFS image to the
> SPI NOR flash and boot from it, and I suspect it's because U-Boot and Linux report different
> eraseblock sizes.
> >
> >
> > On the ZCU102 is a dual-parallel configuration of two MT25QU512ABB SPI NOR flash
> parts. On my board is a dual-parallel configuration of two MT25QL01GBBB SPI NOR flash
> parts.
> >
> >
> > Building u-boot-xlnx and linux-xlnx with meta-xilinx 2017.3 (with some patches of our
> own) we booted the ZCU102 and were able to flash a UBIFS image to the QSPI flash. The
> part's datasheet indicates the block size is 64KiB, which I suppose means a parallel
> combination of two parts gives an effective "block size" of 128KiB.
> >
> >
> > (ZCU102)
> >
> > U-boot:
> >
> > sf probe 0 0 0
> >
> > SF: Detected n25q512a with page size 512 Bytes, erase size 128 KiB, total 128 MiB
> >
> > Linux:
> >
> > [    2.457935] m25p80 spi0.0: found n25q512a, expected m25p80
> > [    2.463463] m25p80 spi0.0: n25q512a (131072 Kbytes)
> > mtdinfo /dev/mtd0
> > Eraseblock size:                131072 bytes, 128.0 KiB
> > Amount of eraseblocks:          8 (1048576 bytes, 1024.0 KiB)
> >
> > Building u-boot-xlnx and linux-xlnx with meta-xilinx 2018.1 now, targeting the custom
> board, Linux and U-boot seem to disagree about the eraseblock size. U-boot reports 128KiB
> (as I expect) and Linux reports 64KiB.
> >
> >
> > (Custom Board)
> >
> > U-boot:
> >
> > sf probe 0 0 0
> >
> > SF: Detected n25q1024 with page size 512 Bytes, erase size 128 KiB, total 256 MiB
> >
> > Linux:
> >
> > [    3.379723] m25p80 spi0.0: found n25q00, expected m25p80
> > [    3.379942] m25p80 spi0.0: n25q00 (262144 Kbytes)
> > mtdinfo /dev/mtd0
> >
> > Eraseblock size:                65536 bytes, 64.0 KiB
> > Amount of eraseblocks:          4096 (268435456 bytes, 256.0 MiB)
> >
> >
> > I'm not worried about the different part names reported by U-boot and Linux, because they
> map to the same ID number in the U-boot and Linux source code. But I'd like to figure out
> why the eraseblock size differs.
> >
> >
> > Kevin Kruse
> > Design Engineer
> > Integre Technologies, LLC
> 
> > --
> > _______________________________________________
> > meta-xilinx mailing list
> > meta-xilinx at yoctoproject.org
> > https://lists.yoctoproject.org/listinfo/meta-xilinx

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