[meta-xilinx] Ultra96 UART

Wed Oct 3 09:21:05 PDT 2018

Hi Simon,

> -----Original Message-----
> From: meta-xilinx-bounces at yoctoproject.org [mailto:meta-xilinx-
> bounces at yoctoproject.org] On Behalf Of simon.goda at doulos.com
> Sent: Wednesday, October 03, 2018 1:19 AM
> To: tom.curran at avnet.com
> Cc: meta-xilinx at lists.yoctoproject.org
> Subject: Re: [meta-xilinx] Ultra96 UART
> 
> Hi Tom
> 
> 
> Thanks for the extra information. I was able to regenerate the HDF with (I think) the
> appropriate changes in the PSU UART configuration (just changing UART1 to
> MIO[0..1], is that all that is required?). I then (eventually) managed to get everything
> to build in Yocto using the new HDF by setting the HDF_PATH appropriately in my
> local.conf.
> 
> 
> With the new boot.bin etc. I see the FSBL output now (a step forward) but nothing
> more - I guess U-Boot is not loading properly from the boot.bin?
> 

Are you using rel-v2018.2 branches?

Is this used while building u-boot? https://github.com/Xilinx/meta-xilinx-tools/blob/rel-v2018.2/recipes-bsp/u-boot/u-boot-xlnx_%25.bbappend

> 
> I am slightly confused as to why this is necessary. Manju from Xilinx said they have
> verified that it works but you are saying that the HDF provided by default in meta-
> xilinx* is incorrect - have I missed something?
> 
> 

We use the mezzanine card for the UART, hence the need for EMIO. 

Thanks,
Manju

> Thanks in advance
> Simon
> 
> 
> -------------------------------------------------------------------
> Date: Fri, 28 Sep 2018 21:24:27 +0000
> From: "Curran, Tom (EM)" <Tom.Curran at Avnet.com
> <mailto:Tom.Curran at Avnet.com> >
> To: "meta-xilinx at lists.yoctoproject.org <mailto:meta-xilinx at lists.yoctoproject.org>
> "
> <meta-xilinx at lists.yoctoproject.org <mailto:meta-xilinx at lists.yoctoproject.org> >
> Subject: Re: [meta-xilinx] Ultra96 UART
> Message-ID:
> <0434C4D44760FB40AAFB554C7C241CAF107960EB at CMX039USMB.AVNET.COM
> <mailto:0434C4D44760FB40AAFB554C7C241CAF107960EB at CMX039USMB.AVNET.
> COM> >
> Content-Type: text/plain; charset="utf-8"
> 
> Yes, the user STDIN/STDOUT UART is psu_uart_1 in the image that gets built via
> meta-xilinx, etc., BUT the UART is mapped out through EMIO to the low speed
> expansion header:
> 
> #HD_GPIO_5 on FPGA / Connector pin 13 / UART1_rxd set_property PACKAGE_PIN
> G5 [get_ports UART1_rxd]
> #HD_GPIO_4 on FPGA / Connector pin 11 / UART1_txd set_property PACKAGE_PIN
> F6 [get_ports UART1_txd]
> 
> You can get a look at the hardware platform by installing the posted PetaLinux BSP
> for the Ultra96 board:
> https://www.xilinx.com/member/forms/download/xef.html?filename=xilinx-
> ultra96-reva-v2018.2-final.bsp
> <https://www.xilinx.com/member/forms/download/xef.html?filename=xilinx-
> ultra96-reva-v2018.2-final.bsp>
> 
> See Xilinx UG1144 for the BSP install instructions:
> http://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_2/ug1144-
> petalinux-tools-reference-guide.pdf
> <http://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_2/ug1144
> -petalinux-tools-reference-guide.pdf>
> 
> To use the Avnet USB UART/JTAG adapter the UART needs to be changed from EMIO
> to MIO[0:1] in the PSU config of the Vivado design.  Then it should be possible to
> regenerate the hdf file and drop it in the correct folder and run a new bitbake build.
> 
> --Tom
> 
> 
> From: meta-xilinx-bounces at yoctoproject.org <mailto:meta-xilinx-
> bounces at yoctoproject.org>  [mailto:meta-xilinx-bounces at yoctoproject.org
> <mailto:meta-xilinx-bounces at yoctoproject.org> ] On Behalf Of Manjukumar
> Harthikote Matha
> Sent: Wednesday, September 26, 2018 11:17 AM
> To: Tomas Thoresen <tomast at xilinx.com <mailto:tomast at xilinx.com> >;
> simon.goda at doulos.com <mailto:simon.goda at doulos.com> ; meta-
> xilinx at lists.yoctoproject.org <mailto:meta-xilinx at lists.yoctoproject.org>
> Subject: Re: [meta-xilinx] Ultra96 UART
> 
> Hi,
> 
> Yes it should be psu_uart_1. Please use rel-v2018.3 branches from github.com/xilinx
> tree, we have verified and it works.
> https://github.com/Xilinx/meta-xilinx-tools/blob/rel-
> v2018.2/classes/xsctyaml.bbclass#L15-L16 <https://github.com/Xilinx/meta-xilinx-
> tools/blob/rel-v2018.2/classes/xsctyaml.bbclass#L15-L16>
> 
> You can use repo command to get the release branches
> http://www.wiki.xilinx.com/How%20to%20build%20images%20through%20yocto
> <http://www.wiki.xilinx.com/How%20to%20build%20images%20through%20yocto>
> 
> Thanks,
> Manju
> 
> From: meta-xilinx-bounces at yoctoproject.org <mailto:meta-xilinx-
> bounces at yoctoproject.org> <mailto:meta-xilinx-bounces at yoctoproject.org
> <mailto:meta-xilinx-bounces at yoctoproject.org> > [mailto:meta-xilinx-
> bounces at yoctoproject.org <mailto:meta-xilinx-bounces at yoctoproject.org> ] On
> Behalf Of Tomas Thoresen
> Sent: Wednesday, September 26, 2018 2:04 AM
> To: simon.goda at doulos.com <mailto:simon.goda at doulos.com>
> <mailto:simon.goda at doulos.com <mailto:simon.goda at doulos.com> >; meta-
> xilinx at lists.yoctoproject.org <mailto:meta-xilinx at lists.yoctoproject.org>
> <mailto:meta-xilinx at lists.yoctoproject.org <mailto:meta-
> xilinx at lists.yoctoproject.org> >
> Subject: Re: [meta-xilinx] Ultra96 UART
> 
> Hi Simon,
> 
> If I?m not mistaking, I believe it uses uart1 instead of uart0...
> 
> So, something like this:
> 
> YAML_BSP_CONFIG[stdin]="set,psu_uart_1"
> YAML_BSP_CONFIG[stdout]="set,psu_uart_1"
> 
> 
> Hope this helps.
> 
> Cheers,
> 
> Tomas
> 
> From: meta-xilinx-bounces at yoctoproject.org <mailto:meta-xilinx-
> bounces at yoctoproject.org> <mailto:meta-xilinx-bounces at yoctoproject.org
> <mailto:meta-xilinx-bounces at yoctoproject.org> > [mailto:meta-xilinx-
> bounces at yoctoproject.org <mailto:meta-xilinx-bounces at yoctoproject.org> ] On
> Behalf Of simon.goda at doulos.com <mailto:simon.goda at doulos.com>
> <mailto:simon.goda at doulos.com <mailto:simon.goda at doulos.com> >
> Sent: 26 September 2018 09:48
> To: meta-xilinx at lists.yoctoproject.org <mailto:meta-xilinx at lists.yoctoproject.org>
> <mailto:meta-xilinx at lists.yoctoproject.org <mailto:meta-
> xilinx at lists.yoctoproject.org> >
> Subject: [meta-xilinx] Ultra96 UART
> 
> Hi
> 
> I am trying to get a meta-xilinx/meta-xilinx-tools build (using versions Rocko & rel-
> v2018.2) to boot on an Ultra96 board. Following the various bits of guidance from
> this list I have successfully built, and have all the files I would expect in
> tmp/deploy/images/.
> 
> The files do not seem to boot - or at least I don't see anything on the serial (via the
> Avnet serial to USB dongle for the Ultra96).
> 
> I have read on another forum (http://zedboard.org/content/j6-serial-port-appears-
> not-be-working <http://zedboard.org/content/j6-serial-port-appears-not-be-
> working> ) that the default config of the FSBL for the Ultra96 board does not
> configure the UART properly and indeed using a 'hacked' boot.bin which has been
> 'fixed' from that forum entry I can boot the board and see output on the UART.
> 
> My questions are:
> 
> - Has anyone else successfully booted an Ultra96 using meta-xilinx/meta-xilinx-
> tools?
> - If so, did you see anything on the UART? Were any changes made to the FSBL
> configuration to achieve this?
> 
> Any comments or guidance gratefully received!
> 
> Thanks & regards
> Simon Goda
> 
> 
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