[meta-xilinx] Bitstream/Boot.bin/etc - Providers/Virtual targets

Mon Mar 17 23:50:10 PDT 2014

On 03/17/2014 10:47 PM, Oleg K Dzhimiev wrote:
> Mike,
>
> Could you try this image -
> https://sourceforge.net/p/elphel/ezynq/ci/master/tree/images/zc706/ ?
> Works on the zc706 rev1.1, the jumper settings are the same as yours - 00110,
> uart is via mini usb cable.

Mine claims to be a ref 1.2 board. It outputs the following with your boot.bin 
and u-boot.img:

Udevcfg.PS_VERSION=30800100
slcr.PSS_IDCODE=23731093
DDRC registers after DCI/DDR initialization
DDRC registers
f8006000: 00000081 00001081 03c0780f 02001001 00014001 0004281b 452440d2 7202387
f8006040: fff00000 0f666666 0003c248 00000001 77010800 00000001 00000101 0000502

f8006080: -------- -------- -------- -------- -------- -------- -------- ------6

f80060c0: -------- 00000000 00000000 00000000 00000000 00000000 00000000 0000000

f8006100: -------- -------- -------- -------- -------- 00000000 40000001 4000000
f8006140: 00000035 00000035 00000035 00000035 00000040 00000000 00000000 0000000
f8006180: 00000040 00000040 00000040 00000080 10020000 0000bc82

f8006180: -------- -------- -------- -------- -------- -------- -------- ------c
f80061c0: 00000020 00000000 00000000 0000441c 0000441c 0000441c 0000441c 0000007

f8006200: 00153042 00000000 000803ff 000803ff 000803ff 000803ff 000003ff 000003f

f8006280: -------- -------- -------- -------- -------- 00000000 00000000 0000006

Training results registers state after DDRC initialization
BIST errors from reg_6c (1 bit per slice) = 0x00000000
BIST errors from reg_6d (1 bit per slice) = 0x00000000

Adjusted always:
FIFO WE DLL SLICE 0 = 0x0000003d
FIFO WE DLL SLICE 1 = 0x0000003d
FIFO WE DLL SLICE 2 = 0x0000003f
FIFO WE DLL SLICE 3 = 0x00000038

Adjusted when CONFIG_EZYNQ_DDR_TRAIN_READ_GATE is set :
FIFO WE ratio SLICE 0 = 0x000000b0
FIFO WE ratio SLICE 1 = 0x000000af
FIFO WE ratio SLICE 2 = 0x000000b8
FIFO WE ratio SLICE 3 = 0x0000009e

Adjusted when CONFIG_EZYNQ_DDR_TRAIN_DATA_EYE is set :
DQS ratio from Read Data Eye Training SLICE 0 = 0x00000000
DQS ratio from Read Data Eye Training SLICE 1 = 0x00000000
DQS ratio from Read Data Eye Training SLICE 2 = 0x00000000
DQS ratio from Read Data Eye Training SLICE 3 = 0x00000000

Adjusted when CONFIG_EZYNQ_DDR_TRAIN_WRITE_LEVEL is set :
DQ write data ratio from Write Leveling Training SLICE 0 = 0x00000000
DQ write data ratio from Write Leveling Training SLICE 1 = 0x00000000
DQ write data ratio from Write Leveling Training SLICE 2 = 0x00000000
DQ write data ratio from Write Leveling Training SLICE 3 = 0x00000000

Adjusted when CONFIG_EZYNQ_DDR_TRAIN_WRITE_LEVEL is set :
DQS write ratio from Write Leveling Training SLICE 0 = 0x00000040
DQS write ratio from Write Leveling Training SLICE 1 = 0x0000000c
DQS write ratio from Write Leveling Training SLICE 2 = 0x00000020
DQS write ratio from Write Leveling Training SLICE 3 = 0x00000000

Adjusted when CONFIG_EZYNQ_DDR_TRAIN_WRITE_LEVEL is set :
Delay for write DQS slave DLL SLICE 0 = 0x00000000
Delay for write DQS slave DLL SLICE 1 = 0x00000000
Delay for write DQS slave DLL SLICE 2 = 0x00000000
Delay for write DQS slave DLL SLICE 3 = 0x00000000

Adjusted when CONFIG_EZYNQ_DDR_TRAIN_WRITE_LEVEL is set :
Delay for write DQ slave DLL SLICE 0 = 0x00000022
Delay for write DQ slave DLL SLICE 1 = 0x00000022
Delay for write DQ slave DLL SLICE 2 = 0x00000022
Delay for write DQ slave DLL SLICE 3 = 0x00000022

Adjusted always:
Delay for read DQ slave DLL SLICE 0 = 0x0000001c
Delay for read DQ slave DLL SLICE 1 = 0x0000001c
Delay for read DQ slave DLL SLICE 2 = 0x0000001c
Delay for read DQ slave DLL SLICE 3 = 0x0000001c

Delay all Slave DLLs for Master DLL 1 = 0x00000089
Delay all Slave DLLs for Master DLL 0 = 0x0000008a
Master DLL 1 locked = 0x00000001
Master DLL 0 locked = 0x00000001

Master DLL Output filter locked (+2 - coarse, +1 - fine = 0x00000000
Values applied to PHY_CTRL Slave DLL = 0x00000000
PHY Control Master DLL status (locked) = 0x00000000
Values from Master DLL Output Filter = 0x0000000b
Values applied to Master DLL Output Filter = 0x0000027f

Delay values applied to read DQS slave DLL = 0x00000044
Values applied to Master DLL Output Filter = 0x00000027
OCM memory data
00000000: ea000013 e59ff014 e59ff014 e59ff014 e59ff014 e59ff014 e59ff014 e59ff08
00000040: 00000000 00009d84 00009e94 00009d84 0badc0de eb000014 e10f0000 e200100
00000080: e59f0064 ee0c0f10 eb000008 eb000015 eb000480 ee070f15 ee070f9a ee070f5
000000c0: ee070f9a ee070f95 ee110f10 e3c00a02 e3c00007 e3800002 e3800b02 e3800a5
00000100: ee073fd5 ee073f9a ee073f95 e12fff1e e12fff1e e12fff1e e92d4008 eb00040
00000140: e3811603 e3811603 ee011f50 f57ff06f eef81a10 e3811101 eee81a10 e1a0f05
00000180: e92d4038 e3a0333e e5933120 e7e54453 e7e13253 e2433002 e3530001 83a0300
000001c0: e7920103 eaffffff ebffffe4 e3540000 03a04001 e1a01004 e08000a4 e1a0500
00000200: e5933154 e59f2034 e7e54453 e2033030 e7d23223 e3530002 959f2024 859f000
00000240: 000076de 00007618 f8000108 e92d4008 eb000366 ebffffc9 eb000359 e3a0004
00000280: e5832108 e59f23bc e5832100 e2422a09 e5832104 e2422a02 e5832108 e59f239
000002c0: e5832104 e2422a02 e5832108 e59f2384 e5832120 e59f2380 e5832124 e59f234

DDR memory data
04000000: ea000013 e59ff014 e59ff014 e59ff014 e59ff014 e59ff014 e59ff014 e59ff08
04000040: 00000000 00009d84 00009e94 00009d84 0badc0de eb000014 e10f0000 e200100
04000080: e59f0064 ee0c0f10 eb000008 eb000015 eb000480 ee070f15 ee070f9a ee070f5
040000c0: ee070f9a ee070f95 ee110f10 e3c00a02 e3c00007 e3800002 e3800b02 e3800a5
04000100: ee073fd5 ee073f9a ee073f95 e12fff1e e12fff1e e12fff1e e92d4008 eb00040
04000140: e3811603 e3811603 ee011f50 f57ff06f eef81a10 e3811101 eee81a10 e1a0f05
04000180: e92d4038 e3a0333e e5933120 e7e54453 e7e13253 e2433002 e3530001 83a0300
040001c0: e7920103 eaffffff ebffffe4 e3540000 03a04001 e1a01004 e08000a4 e1a0500
04000200: e5933154 e59f2034 e7e54453 e2033030 e7d23223 e3530002 959f2024 859f000
04000240: 000076de 00007618 f8000108 e92d4008 eb000366 ebffffc9 eb000359 e3a0004
04000280: e5832108 e59f23bc e5832100 e2422a09 e5832104 e2422a02 e5832108 e59f239
040002c0: e5832104 e2422a02 e5832108 e59f2384 e5832120 e59f2380 e5832124 e59f234

Memories data checksums:
Read 00000001: OCM= 0x92a51516  DDR= 0x92a51516
Read 00000002: OCM= 0x92a51516  DDR= 0x92a51516
Read 00000003: OCM= 0x92a51516  DDR= 0x92a51516

12345678
Copying ps7_init.c/h from hw project is NOT REQUIRED
mmc boot
reading fpga.bin
sdhci_transfer_data: Error detected in status(0x208000)!
Error reading cluster
spl: error reading image fpga.bin, err - -1
reading system.dtb
spl: error reading image system.dtb, err - -1
reading u-boot.img
spl: error reading image u-boot.img, err - -1
### ERROR ### Please RESET the board ###

Met vriendelijke groet / kind regards,

Mike Looijmans

TOPIC Embedded Systems
Eindhovenseweg 32-C, NL-5683 KH Best
Postbus 440, NL-5680 AK Best
Telefoon: (+31) (0) 499 33 69 79
Telefax:  (+31) (0) 499 33 69 70
E-mail: mike.looijmans at topic.nl
Website: www.topic.nl

Please consider the environment before printing this e-mail