[meta-xilinx] 2nd ethernet port not detected

[Edward Wingate]

On Thu, Oct 15, 2015 at 6:25 AM, Mike Looijmans <mike.looijmans at topic.nl> wrote:
> On 15-10-15 09:35, Edward Wingate wrote:
>> On Mon, May 18, 2015 at 10:16 PM, Mike Looijmans <mike.looijmans at topic.nl> wrote:
>>> The internal PL PHY is on the same MDIO bus as the external one.
>>> The eth0 and eth1 phys are on different busses.
>>
>> Mike, If you would, can you please provide some clarification on this?
>> When you say the "internal PL PHY", are you referring to the
>> GMII-to-RGMII PL IP?  What is the "external one" that is on the same
>> MDIO bus?   Is the "external one" different from the eth0 PHY chip and
>> eth1 PHY chip?
>
> Yes, the internal one is in logic in the IP. So there are TWO phys on that
> bus, and they need a unique address each.

OK, then they do have unique address, though one is address 0.
I'll see how it works with address 1.

> As the datasheet should have explained, "0" is not a valid PHY address. So
> that does not leave many options. "0" is actually the "broadcast" address on
> the MDIO bus, so all phys will respond to it. Which makes it work with just
> one PHY, but with multiple PHYs on the MDIO bus this will not work.

The datasheet itself never mentions 0 as being the broadcast address.
I wonder if the GMII-to_RGMII IP responds to 0, or only its assigned
PHY address.